MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 621

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

14.1.3
The LBC provides one GPCM, one SDRAM machine, and three UPMs for the local bus, with no
restriction on how many of the eight banks (chip selects) can be programmed to operate with any given
machine. When a memory transaction is dispatched to the LBC, the memory address is compared with the
address information of each bank (chip select). The corresponding machine assigned to that bank (GPCM,
SDRAM, or UPM) then takes ownership of the external signals that control the access and maintains
control until the transaction ends. Thus, with the LBC in GPCM, SDRAM, or UPM mode, only one of the
eight chip selects is active at any time for the duration of the transaction.
14.1.3.1
The LBC supports ratios of 4, 8, and 16 between the faster system (CCB) clock and the slower external
bus clock (LCLK[0:2]). This ratio is software programmable through the clock ratio register
(LCRR[CLKDIV]). In addition to establishing the frequency of the external local bus clock, CLKDIV also
affects the resolution of signal timing shifts in GPCM mode and the interpretation of UPM array words in
UPM mode. The bus clock is driven identically onto signals LCLK[0:2] to allow the clock load to be
shared equally across a pair of signal nets, thereby enhancing the edge rates of the bus clock.
Freescale Semiconductor
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— Four byte-write-enable signals (LWE[0:3])
— Output enable signal (LOE)
— External access termination signal (LGTA)
Three user-programmable machines (UPMs)
— Programmable-array-based machine controls external signal timing with a granularity of up to
— User-specified control-signal patterns run when an internal master requests a single-beat or
— UPM refresh timer runs a user-specified control signal pattern to support refresh
— User-specified control-signal patterns can be initiated by software
— Each UPM can be defined to support DRAM devices with depths of 64, 128, 256, and 512
— Support for 8-, 16-, 32-bit devices
— Page mode support for successive transfers within a burst
— Internal address multiplexing supporting 64-, 128-, 256-, and 512-Kbyte, and 1-, 2-, 4-, 8-, 16-,
Optional monitoring of transfers between local bus internal masters and local bus slaves (local bus
error reporting)
Support for phase-locked loop (PLL) with software-configurable bypass for low frequency bus
clocks
one-quarter of an external bus clock period
burst read or write access.
Kbytes, and 1, 2, 4, 8, 16, 32, 64, 128, and 256 Mbytes
32-, 64-, 128-, and 256-Mbyte page banks
Modes of Operation
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
LBC Bus Clock and Clock Ratios
Local Bus Controller
14-3