MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 275

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

7.2.3
The e500 core connects to the L2 cache and the system interface through the high-speed core complex bus
(CCB). The e500 core and the L2 cache connect to the rest of the integrated device through the e500
coherency module (ECM).
e500 core can simultaneously read 128 bits of data from the L2/SRAM, read 64 bits of data from the
system interface, and write 128 bits of data to the L2/SRAM and/or system interface.
Freescale Semiconductor
(single 128-KB SRAM if L2SIZ=256 KB)
(single 64-KB SRAM if L2SIZ=256 KB)
(single 64-KB SRAM if L2SIZ=256 KB)
(single 32-KB SRAM if L2SIZ=256 KB)
(single 32-KB SRAM if L2SIZ=256 KB)
(two 128-KB SRAM if L2SIZ=256 KB)
Two quarters of the array are SRAMs
One eighth of the array is an SRAM
Two eighths of the array are SRAM
One quarter of the array is SRAM
Both halves of array are SRAM
One half of array is an SRAM
Description
Connection of the On-Chip Memory to the System
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 7-2. Way Selection for SRAM Accesses (continued)
Figure 7-5
L2SRAM
shows the data connections of the e500 core and L2/SRAM. The
010
011
100
101
110
111
BAR 0 Hit
1
1
0
1
1
0
1
1
0
BAR 1 Hit
0
0
1
0
0
1
0
0
1
Addr[18–20]
L2 Look-Aside Cache/SRAM
x00
x01
x10
x11
x00
x01
x10
x11
x00
x01
x10
x11
xx0
xx1
xx0
xx1
xx0
xx1
—
—
—
Way Select
0
1
2
3
0
1
2
3
4
5
6
7
0
1
0
1
2
3
0
0
1
7-7