MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 261
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
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6.13.3
6.13.4
6.14
Freescale Semiconductor
SPR 312 (IAC1); SPR 313 (IAC2)
SPR 316 (DAC1); SPR 317 (DAC2)
Reset
Reset
Reset
Reset
SPR: 512
Bits
32
33
W
W
W
W
R
R
R
R
SOVH OVH FGH FXH FINVH FDBZH FUNFH FOVFH
32
32
SOV
32
48
Name
SOVH
OVH
Signal Processing and Embedded Floating-Point Status
and Control Register (SPEFSCR)
OV
Instruction Address Compare Registers (IAC1–IAC2)
Data Address Compare Registers (DAC1–DAC2)
33
49
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 6-56. Signal Processing and Embedded Floating-Point Status and
until it is cleared by an mtspr[SPEFSCR].
Integer overflow high. An overflow occurred in the upper half of the register while executing a SPE integer
instruction
Summary integer overflow high. Set whenever an instruction (except mtspr) sets OVH. SOVH remains set
FG
34
50
Figure 6-54. Instruction Address Compare Registers (IAC1–IAC2)
High-Word Error Bits
Figure 6-55. Data Address Compare Registers (DAC1–DAC2)
FX
35
51
FINV
36
52
Table 6-39. SPEFSCR Field Descriptions
FDBZ
37
53
Control Register (SPEFSCR)
FUNF
38
54
Instruction address
FOVF — FINXE FINVE FDBZE FUNFE FOVFE
Data address
39
55
All zeros
All zeros
All zeros
All zeros
40
56
Function
—
41
57
FINXS FINVS FDBZS FUNFS FOVFS
42
58
Enable Bits
43
59
Status Bits
Access: Supervisor read/write
Access: Supervisor read/write
44
60
Core Register Summary
45
61
Access: User mixed
46
62
FRMC
61 62 63
MODE
—
47
63
6-45
63
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