MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 404

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Programmable Interrupt Controller
10.2.2
Table 10-5
10-8
IRQ_OUT
IRQ[0:11]
Signal
MCP
UDE
provides detailed descriptions of the external PIC signals.
I/O
O
I
I
I
Detailed Signal Descriptions
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Interrupt request 0–11. The polarity and sense of each of these signals is programmable. All of these inputs
can be driven asynchronously. The interrupt request signals IRQn may share PIC external interrupt registers
with PCI Express INTx signaling. See
Interrupt request out. Active-low, open drain. When the PIC is programmed in pass-through mode, this output
reflects the raw interrupts generated by on-chip sources. See
details.
Machine check processor. Assertion causes a machine check interrupt to the e500 core. Note that if the e500
core is not configured to process machine check interrupts (MSR[ME] = 0), assertion of MCP causes a
checkstop condition. Note that internal sources for the internal core_mcp signal can also cause a machine
check interrupt to the processor core, as described in
(MCPSUMR),” Table 10-1
Unconditional debug event. Assertion signal causes an unconditional debug exception to the e500 core.
Meaning
Meaning
Meaning
Meaning
Timing Assertion—All of these inputs can be asserted completely asynchronously.
Timing Because external interrupts are asynchronous with respect to the system clock, both assertion and
Timing Assertion—May occur at any time, asynchronous to any clock.
Timing Assertion—May occur at any time, asynchronous to any clock.
State
State
State
State
Table 10-5. Interrupt Signals—Detailed Signal Descriptions
Asserted—When an external interrupt signal is asserted (according to the programmed polarity),
Negated—There is no incoming interrupt from that source.
Negation—Interrupts programmed as level-sensitive must remain asserted until serviced.
Asserted—At least one interrupt is currently being signaled to the external system.
Negated—Indicates no interrupt source currently routed to IRQ_OUT.
negation of IRQ_OUT occurs asynchronously with respect to the interrupt source. All timing given
here is approximate.
Assertion—Internal interrupt source: 2 CCB clock cycles after interrupt occurs.
Negation—Follows interrupt source negation with the following delay:
Asserted—Integrated logic should initiate a machine check interrupt or enter the checkstop state
Negated—Machine check handling is not being requested by the external system.
Negation—Because MCP is edge-triggered, it can be negated one clock after its assertion.
Asserted—Indicates that integrated logic should initiate an unconditional debug event interrupt to
Negated—Indicates that unconditional debug event handling is not being requested by UDE.
Negation—Should remain asserted until software in the unconditional debug event interrupt
the priority is checked by the PIC unit, and the interrupt is conditionally passed to the
processor. In pass-through mode, only interrupts detected on IRQ0 are passed directly to the
processor core.
External interrupt source: 4 cycles after interrupt occurs.
Message interrupts: 2 cycles after write to message register.
Internal interrupt: 2 CCB clock cycles
External interrupt: 4 cycles.
Message interrupts: 2 cycles after message register cleared.
as directed by the MSR.
the processor core.
handler causes the external device asserting the UDE signal to negate it.
and
Table
10-2.
Section 10.4.6, “PCI Express
Description
Section 19.4.1.14, “Machine Check Summary Register
Section 10.1.4, “Modes of
INTx,” for more information.
Freescale Semiconductor
Operation,” for more