MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 57

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

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Freescale Semiconductor
MIIMADD Register Definition .......................................................................................... 15-74
MII Mgmt Control Register Definition............................................................................... 15-74
MIIMSTAT Register Definition .......................................................................................... 15-75
MII Mgmt Indicator Register Definition ............................................................................ 15-75
Interface Status Register Definition .................................................................................... 15-76
MAC Station Address Part 1 Register Definition ............................................................... 15-77
MAC Station Address Part 2 Register Definition ............................................................... 15-77
MAC Exact Match Address n Part 1 Register Definition ................................................... 15-78
MAC Exact Match Address x Part 2 Register Definition ................................................... 15-78
Transmit and Receive 64-Byte Frame Register Definition................................................. 15-79
Transmit and Receive 65- to 127-Byte Frame Register Definition .................................... 15-80
Transmit and Received 128- to 255-Byte Frame Register Definition ................................ 15-80
Transmit and Received 256- to 511-Byte Frame Register Definition................................. 15-81
Transmit and Received 512- to 1023-Byte Frame Register Definition .............................. 15-81
Transmit and Received 1024- to 1518-Byte Frame Register Definition ............................ 15-82
Transmit and Received 1519- to 1522-Byte VLAN Frame Register Definition ................ 15-82
Receive Byte Counter Register Definition.......................................................................... 15-83
Receive Packet Counter Register Definition ...................................................................... 15-83
Receive FCS Error Counter Register Definition................................................................. 15-84
Receive Multicast Packet Counter Register Definition ...................................................... 15-84
Receive Broadcast Packet Counter Register Definition ..................................................... 15-85
Receive Control Frame Packet Counter Register Definition .............................................. 15-85
Receive Pause Frame Packet Counter Register Definition ................................................. 15-86
Receive Unknown OPCode Packet Counter Register Definition ....................................... 15-86
Receive Alignment Error Counter Register Definition....................................................... 15-87
Receive Frame Length Error Counter Register Definition ................................................. 15-87
Receive Code Error Counter Register Definition ............................................................... 15-88
Receive Carrier Sense Error Counter Register Definition .................................................. 15-88
Receive Undersize Packet Counter Register Definition ..................................................... 15-89
Receive Oversize Packet Counter Register Definition ....................................................... 15-89
Receive Fragments Counter Register Definition ................................................................ 15-90
Receive Jabber Counter Register Definition....................................................................... 15-90
Receive Dropped Packet Counter Register Definition ....................................................... 15-91
Transmit Byte Counter Register Definition ........................................................................ 15-91
Transmit Packet Counter Register Definition ..................................................................... 15-92
Transmit Multicast Packet Counter Register Definition ..................................................... 15-92
Transmit Broadcast Packet Counter Register Definition .................................................... 15-93
Transmit Pause Control Frame Counter Register Definition .............................................. 15-93
Transmit Deferral Packet Counter Register Definition....................................................... 15-94
Transmit Excessive Deferral Packet Counter Register Definition...................................... 15-94
Transmit Single Collision Packet Counter Register Definition .......................................... 15-95
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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