MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 168

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Reset, Clocking, and Initialization
Figure 4-5
4.4.3
Various device functions are initialized by sampling certain signals during the assertion of HRESET. The
values of all these signals are sampled into registers while HRESET is asserted. These inputs are to be
pulled high or low by external resistors. During HRESET, all other signal drivers connected to these
signals must be in the high-impedance state.
4-10
HRESET_REQ
1
POR Configs
PLL Configs
Multiplexed with TRIG_OUT.
11. When the boot sequencer completes the PCI interface is released to accept external requests, and
12. The ASLEEP signal negates synchronized to a rising edge of SYSCLK, indicating the ready state.
HRESET
SRESET
SYSCLK
TRESET
ASLEEP
READY
the boot vector fetch by the e500 core is allowed to proceed unless processor booting is further held
off by POR configuration inputs as described in
MPC8533E is now in its ready state.
The ready state is also indicated by the assertion of READY/TRIG_OUT if TOSR[SEL] = 000. In
this case, READY is asserted with the same rising edge of SYSCLK, to indicate that the device has
reached its ready state. See
information on this register.
Asserting READY allows external system monitors to know basic device status, for example,
exactly when it emerges from reset, or if the device is in a low-power mode. For more information
on the debug functions of TRIG_OUT, see
information about power management states, see
shows a timing diagram of the POR sequence.
Power-On Reset Configuration
1
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
(high impedance)
(High Impedance)
(High Impedance)
Figure 4-5. Power-On Reset Sequence
Section 21.3.4.1, “Trigger Out Source Register (TOSR),”
Section 21.3.4, “Trigger Out Function.”
Section 4.4.3.7, “CPU Boot Configuration.”
Section 19.4.1, “Register Descriptions.”
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