MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 704

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
For refresh, the memory controller supplies auto refresh to SDRAM according to the time interval
specified in LSRT and MPTPR as follows:
This represents the time period required between refreshes. When the refresh timer expires, the memory
controller issues a CBR to each chip select. Each CBR is separated by one clock. A refresh timing diagram
for multiple chip selects is shown in
During a memory transaction dispatched to the local bus, the memory controller compares the memory
address with the address information of each chip select (programmed with BRn and ORn). If the
comparison matches a chip select that is controlled by SDRAM, the memory controller requests service to
the local bus SDRAM machine, depending on the information in BRn. Although multiple chip selects may
be programmed for SDRAM, only one chip select is active at any given time; thus, multiple chip selects
can share the same SDRAM machine.
14.5.4.2
Table 14-32
The data port size is programmable, but the following examples use all 32 bits of the local bus. The 32-bit
port size requires 4 SDRAM devices (with 8-bit I/O ports) connected in parallel to a single chip select. If
128-Mbit devices are used, 1 chip select provides 128-Mbit/device × 4 devices = 64 Mbytes. If 4 chip
selects are programmed for SDRAM use, the result is 64 Mbytes × 4 = 256 Mbytes. If 256-Mbit SDRAM
devices are used, the total available memory is 512 Mbytes. Consequently, 512-Mbit devices allow for
1 Gbyte.
Although there is no technical difficulty in supporting multiple chip select configurations, in practice, the
user may want to maximize the amount of SDRAM assigned to each chip select to minimize cost.
14-86
SDRAM
I/O Port
Column
Device
Bank
Row
summarizes information based on typical SDRAM data sheets.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Maximum Amount of SDRAM Supported
12
10
x4
4
x8
12
64-Mbit
4
9
x16
12
4
8
x32
11
4
8
Table 14-32. Typical SDRAM Devices
Refresh Period
Figure 14-52
12
11
x4
4
128-Mbit
12
10
x8
4
=
x16
12
4
9
LSRTx MPTPR PTP
-----------------------------------------------------------------
in
System Frequency
Section 14.4.3.11.1, “SDRAM Refresh Timing.”
x32
12
4
8
(
13
11
x4
4
[
256-Mbit
x8
13
10
4
]
)
x16
13
4
9
x32
13
4
8
13
12
x4
4
Freescale Semiconductor
512-Mbit
11
x8
13
4
x16
10
13
4
x32
—
—
4