MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 788

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15.5.3.3.8
RQFPR (see
filer table. The table entries are described in greater detail in
word accessed via RQFPR is defined by the current value of RQFAR.
describe the fields of the RQFPR register according to property ID.
15-58
Offset eTSEC1:0x2_433C; eTSEC3:0x2_633C
Reset
Reset
25–26
28–31
Bit
27
Offset eTSEC1:0x2_433C; eTSEC3:0x2_633C;
Reset
W
W
R
R
W
R
EBC
16
Name
0
CMP
PID
0
—
Figure
Figure 15-29. Receive Queue Filer Table Property IDs 0, 2–15 Register Definition
VLN
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
17
Receive Queue Filer Table Property Register (RQFPR)
Comparison operation to perform on the RQPROP entry at this index when PID > 0. The property value
extracted by the frame parser is masked by the 32-bit mask_register prior to comparison against RQPROP.
However, the property value is not permanently altered by the value in mask_register . By default,
mask_register is initialized to 0xFFFF_FFFF before each frame is processed.
In the case where PID = 0, CMP is interpreted as follows:
00/01 Filer mask_register is set to all 32 bits of RQPROP, and this entry always matches .
10/11 Filer mask_register is set to all 32 bits of RQPROP, and this entry always fails to match .
In the case where PID > 0, CMP is interpreted as follows (& is bit-wise AND operator):
00 property [PID] & mask_register = RQPROP
01 property [PID] & mask_register >= RQPROP
10 property [PID] & mask_register != RQPROP
11 property [PID] & mask_register < RQPROP
Reserved, should be written with zero.
Property identifier. The value in the RQPROP entry at this index is interpreted according to PID (see
Table
Figure 15-30. Receive Queue Filer Table Property ID1 Register Definition
CFI
15-29) is accessed to read or write the RQPROP words in entries of the receive queue
15-33).
18
JUM
19
Table 15-32. RQFCR Field Descriptions (continued)
IPF
20
FIF
21
IP4
22
IP6
23
All zeros
All zeros
RQPROP
All zeros
—
Description
ICC
24
Section 15.6.5.1, “Receive Queue Filer.”
ICV
25
TCP
26
Figure 15-29
UDP
27
28
Freescale Semiconductor
and
—
Access: Read/Write
Access: Read/Write
Figure 15-30
29
PER
30
EER
The
15
31
31