MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 394

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DDR Memory Controller
9.6.2
After configuration of all parameters is complete, system software must set
DDR_SDRAM_CFG[MEM_EN] to enable the memory interface. Note that 200 μs must elapse after
DRAM clocks are stable (DDR_SDRAM_CLK_CNTL[CLK_ADJUST] is set and any chip select is
enabled) before MEM_EN can be set, so a delay loop in the initialization code may be necessary if
software is enabling the memory controller. If DDR_SDRAM_CFG[BI] is not set, the DDR memory
controller will conduct an automatic initialization sequence to the memory, which will follow the memory
specifications. If the bypass initialization mode is used, then software can initialize the memory through
the DDR_SDRAM_MD_CNTL register.
9.6.3
This section describes the options offered by this device to support battery-backed main memory.
9.6.3.1
An external voltage sense device can be connected to this device through one of the external interrupt lines
IRQn. The external interrupt from the voltage sensor would then be steered through this device’s
programmable interrupt controller (PIC) to the IRQ_OUT signal. Note that the IRQ_OUT signal must
remain high until power is removed.
9-72
DLL_RST_DIS
Parameter
DQS_CFG
ODT_CFG
BSTOPRE
DDR SDRAM Initialization Sequence
Using Forced Self-Refresh Mode to Implement a Battery-Backed
RAM System
Hardware Based Self-Refresh
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 9-54. Programming Differences Between Memory Types (continued)
DLL Reset Disable
DQS Configuration
ODT Configuration
Burst To Precharge Interval DDR1
Description
DDR2
DDR2
DDR2
DDR2
DDR1
DDR1
DDR1
bypass the DLL reset when exiting self refresh.
Should typically be set to 0, unless it is desired to
bypass the DLL reset when exiting self refresh.
differential strobes will be used
system topology. Typically, if ODT is enabled, then
the internal IOs should be set up for termination
only during reads to DRAM.
application. Auto precharge can be enabled by
setting this field to all 0s.
application. Auto precharge can be enabled by
setting this field to all 0s.
Should typically be set to 0, unless it is desired to
Should be set to 00
Can be set to either 00 or 01, depending on if
Should be set to 00
Can be set for termination at the IOs according to
Can be set to any value, depending on the
Can be set to any value, depending on the
Differences
Freescale Semiconductor
Section/page
9.4.1.12/9-29
9.4.1.8/9-23
9.4.1.8/9-23
9.4.1.8/9-23