MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 27

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Paragraph
Number
15.5.1
15.5.2
15.5.3
15.5.3.1
15.5.3.1.1
15.5.3.1.2
15.5.3.1.3
15.5.3.1.4
15.5.3.1.5
15.5.3.1.6
15.5.3.1.7
15.5.3.1.8
15.5.3.1.9
15.5.3.2
15.5.3.2.1
15.5.3.2.2
15.5.3.2.3
15.5.3.2.4
15.5.3.2.5
15.5.3.2.6
15.5.3.2.7
15.5.3.2.8
15.5.3.2.9
15.5.3.2.10
15.5.3.2.11
15.5.3.3
15.5.3.3.1
15.5.3.3.2
15.5.3.3.3
15.5.3.3.4
15.5.3.3.5
15.5.3.3.6
15.5.3.3.7
15.5.3.3.8
15.5.3.3.9
15.5.3.3.10
15.5.3.3.11
15.5.3.3.12
15.5.3.3.13
15.5.3.4
15.5.3.4.1
Freescale Semiconductor
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Top-Level Module Memory Map ............................................................................ 15-13
Detailed Memory Map............................................................................................. 15-13
Memory-Mapped Register Descriptions.................................................................. 15-22
eTSEC General Control and Status Registers...................................................... 15-22
eTSEC Transmit Control and Status Registers.................................................... 15-36
eTSEC Receive Control and Status Registers ..................................................... 15-48
MAC Functionality.............................................................................................. 15-64
Controller ID Register (TSEC_ID).................................................................. 15-22
Controller ID Register (TSEC_ID2)................................................................ 15-23
Interrupt Event Register (IEVENT) ................................................................ 15-24
Interrupt Mask Register (IMASK) .................................................................. 15-28
Error Disabled Register (EDIS)....................................................................... 15-30
Ethernet Control Register (ECNTRL) ............................................................. 15-31
Pause Time Value Register (PTV) ................................................................... 15-33
DMA Control Register (DMACTRL) ............................................................. 15-34
TBI Physical Address Register (TBIPA) ......................................................... 15-35
Transmit Control Register (TCTRL) ............................................................... 15-36
Transmit Status Register (TSTAT)................................................................... 15-38
Default VLAN Control Word Register (DFVLAN) ........................................ 15-42
Transmit Interrupt Coalescing Register (TXIC).............................................. 15-43
Transmit Queue Control Register (TQUEUE) ................................................ 15-44
TxBD Ring 0–3 Weighting Register (TR03WT)............................................. 15-44
TxBD Ring 4–7 Weighting Register (TR47WT)............................................. 15-45
Transmit Data Buffer Pointer High Register (TBDBPH)................................ 15-46
Transmit Buffer Descriptor Pointers 0–7 (TBPTR0–TBPTR7) ...................... 15-46
Transmit Descriptor Base Address High Register (TBASEH)........................ 15-47
Transmit Descriptor Base Address Registers (TBASE0–TBASE7) ............... 15-48
Receive Control Register (RCTRL) ................................................................ 15-48
Receive Status Register (RSTAT).................................................................... 15-50
Receive Interrupt Coalescing Register (RXIC) ............................................... 15-52
Receive Queue Control Register (RQUEUE) ................................................. 15-53
Receive Bit Field Extract Control Register (RBIFX)...................................... 15-55
Receive Queue Filer Table Address Register (RQFAR) ................................. 15-56
Receive Queue Filer Table Control Register (RQFCR) .................................. 15-57
Receive Queue Filer Table Property Register (RQFPR) ................................. 15-58
Maximum Receive Buffer Length Register (MRBLR) ................................... 15-61
Receive Data Buffer Pointer High Register (RBDBPH) ................................. 15-61
Receive Buffer Descriptor Pointers 0–7 (RBPTR0–RBPTR7) ....................... 15-62
Receive Descriptor Base Address High Register (RBASEH)......................... 15-63
Receive Descriptor Base Address Registers (RBASE0–RBASE7) ................ 15-63
Configuring the MAC ..................................................................................... 15-64
Contents
Title
Number
Page
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