MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 102
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Available stocks
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- MPC8533VTALF PDF datasheet
- MPC8533VTALF PDF datasheet #2
- MPC8533VTALF PDF datasheet #3
- MPC8533VTALF PDF datasheet #4
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- Download datasheet (18Mb)
Overview
1-4
•
•
— On-die termination support when using DDR2
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access via JTAG port
— 2.5-V SSTL_2 compatible I/O (1.8-V SSTL_1.8 for DDR2)
— Support for battery-backed main memory
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture.
— 16 programmable interrupt and processor task priority levels
— 12 discrete external interrupts
— 4 message interrupts with 32-bit messages
— Message shared interrupts
— Connection of an external interrupt controller such as the 8259 programmable interrupt
— Four global high resolution timers/counters that can generate interrupts
— Supports a variety of other internal interrupt sources
— Fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing.
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs.
— Interrupt summary registers allow fast identification of interrupt source.
Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec,
IKE, WTLS/WAP, SSL/TLS, and 3GPP
— Four crypto-channels, each supporting multi-command descriptor chains
— PKEU—public key execution unit
— DEU—Data Encryption Standard (DES) execution unit
— AESU—Advanced Encryption Standard (AES) unit
controller
– Dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
– RSA and Diffie-Hellman; programmable field size up to 2048 bits
– Elliptic curve cryptography with F
– DES, 3DES
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
– Implements the Rijndael symmetric key cipher
– ECB, CBC, CTR, and CCM modes
– 128-, 192-, and 256-bit key lengths
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
511 bits
2
m and F(p) modes and programmable field size up to
Freescale Semiconductor
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