MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 873

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

15.6.3.3
The Ethernet transmitter requires little core intervention. After the software driver initializes the system,
the eTSEC begins to poll the first transmit buffer descriptor (TxBD) in TxBD ring 0 every 512 transmit
clocks. If TxBD[R] is set, and the TxBD ring is scheduled for transmission, the eTSEC begins copying the
associated transmit buffer from memory to its Tx FIFO. The transmitter takes data from the Tx FIFO and
transmits data to the MAC. The MAC transmits the data through the GMII interface to the physical media.
The transmitter, once initialized, runs until the end-of-frame (EOF) condition is detected unless a collision
within the collision window occurs (half-duplex mode) or an abort condition is encountered.
If the user has a frame ready to transmit, setting the DMACTRL[TOD] eliminates waiting for the next poll
and a DMA transfer of the transmit data buffers can begin immediately. The transmission begins once all
data for the frame is loaded into the Tx FIFO or sufficient transmit data (determined by the Tx FIFO
threshold register) is in the Tx FIFO. If the line is not busy, the MAC transmit logic asserts TX_EN and
sends the 7-octet preamble sequence, 1-octet start of frame delimiter, and frame information in that order.
If the line is busy, the controller waits for the carrier sense signal, CRS, to remain inactive for 60 bit times
(60 clocks) and transmission begins after an additional 36 bit times (96 bit times after CRS became active).
In full-duplex mode, because collisions are ignored, frame transmission maintains only the interframe gap
(96 bit times) regardless of CRS.
In half-duplex mode (MACCFG2[Full Duplex] is cleared) the MAC defers transmission if the line is busy
(CRS asserted). Before transmitting, the MAC waits for carrier sense to become inactive, at which point
it then determines if CRS remains negated for 60 clocks. If so, transmission begins after an additional 36
bit times (96 bit times after CRS originally became negated). If CRS continues to be asserted, the MAC
follows a specified back-off procedure and tries to retransmit the frame until the retry limit is reached. Data
stored in the Tx FIFO is re-transmitted in case of a collision. This avoids unnecessary memory traffic.
The transmitter also monitors for an abort condition and terminates the current frame if an abort condition
is encountered. In full-duplex mode the protocol is independent of network activity, and only the transmit
inter-frame gap must be enforced.
The transmitter implements full-duplex flow control. If a flow control frame is received, the MAC does
not service the transmitter’s request to send data until the pause duration is over. If the MAC is currently
sending data after a pause frame has been received and processed, the MAC finishes sending the current
frame, then suspends subsequent frames (except a pause frame) until the pause duration is over. In
addition, the transmitter supports transmission of flow control frames via TCTRL[TFC_PAUSE]. The
transmit pause frame is generated internally based on the PAUSE register that defines the pause value to
be sent. Note that it is possible to send a pause frame while the pause timer has not expired.
The MAC automatically appends FCS (32-bit CRC) bytes to the frame if any of the following values are
set:
Freescale Semiconductor
14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.
15. Clear GRS/GTS bits in DMACTRL (do not change other bits)
16. Enable Tx_EN/Rx_EN in MACCFG1 register
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•
TxBD[PAD/CRC] is set in first TxBD
TxBD[TC] is set in first TxBD
Gigabit Ethernet Frame Transmission
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Enhanced Three-Speed Ethernet Controllers
15-143