MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 607

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MPC8533EVTARJ

Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTARJ

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Figure 13-9
Table 13-13
Freescale Semiconductor
Bits
6–7
0
1
2
3
4
5
Offset 0x503
Reset
Name
NTSB Number of STOP bits.
DLAB Divisor latch access bit.
WLS
EPS
PEN
W
SB
SP
R
shows the bits in the ULCRs.
0x603
describes the fields of the ULCRs.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0 Access to all registers except UDLB, UAFR, and UDMB
1 Ability to access divisor latch least and most significant byte registers and alternate function register
Set break.
0 Send normal UTHR data onto the serial output (SOUT) signal
1 Force logic 0 to be on the SOUT signal. Data in the UTHR is not affected
Stick parity.
0 Stick parity is disabled.
1 If PEN = 1 and EPS = 1, space parity is selected. And if PEN = 1 and EPS = 0, mark parity is selected.
Even parity select. See
0 If PEN = 1 and SP = 0, odd parity is selected.
1 If PEN = 1 and SP = 0, even parity is selected.
Parity enable.
0 No parity generation and checking
1 Generate parity bit as a transmitter, and check parity as a receiver
0 One STOP bit is generated in the transmitted data.
1 When a 5-bit data length is selected, 1∫ STOP bits are generated. When either a 6-, 7-, or 8-bit word length
Word length select. Number of bits that comprise the character length. The word length select values are as
follows:
00 5 bits
01 6 bits
10 7 bits
11 8 bits
DLAB
(UAFR)
is selected, two STOP bits are generated.
0
SB
1
Figure 13-9. Line Control Register (ULCR)
Table 13-13. ULCR Field Descriptions
Table 13-14
SP
2
for more information.
EPS
3
All zeros
Description
PEN
4
NSTB
5
Access: Read/Write
6
WLS
7
DUART
13-13

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