MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 127

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

In this example, it is not necessary to use a local access window to specify the range of memory used for
memory-mapped registers because this is a fixed 1-Mbyte space pointed to by CCSRBAR. See
Section 4.3.1.1.2, “Configuration, Control, and Status Base Address Register (CCSRBAR).”
required to define a local access window to describe the location of the boot ROM because it is in the
default location (see
provides one default TLB entry to access boot code and it allows for accesses within the highest 4 Kbytes
of the low 4 Gbytes of memory. In order for the e500 to access the full 8 Mbytes of default boot space (and
the 1 Mbyte of CCSR space), additional TLB entries must be set up within the e500 MMU for mapping
these regions.
2.2
Four distinct types of translation and mapping operations are performed on transactions in the MPC8533E.
These are as follows:
The local access windows perform target mapping for transactions within the local address space. No
address translation is performed by the local access windows.
Outbound ATMU windows perform the mapping from the local 36-bit address space to the address spaces
of PCI or PCI-Express, for example, which may be much larger than the local space. Outbound ATMU
windows also map attributes such as transaction type or priority level.
Inbound ATMU windows perform the address translation from the external address space to the local
address space, attach attributes and transaction types to the transaction, and also map the transaction to its
target interface. Note that in mapping the transaction to the target interface, an inbound ATMU window
performs a similar function as the local access windows. The target mappings created by an inbound
ATMU must be consistent with those of the local access windows. That is, if an inbound ATMU maps a
transaction to a given local address and a given target, a local access window must also map that same local
address to the same target.
All of the configuration registers that define translation and mapping functions use the concept of
translation or mapping windows, and all follow the same register format.
format of these window definitions.
Freescale Semiconductor
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•
•
•
Translation address
Base address
Window size/attributes
Mapping a local address to a target interface
Assigning attributes to transactions
Translating the local 36-bit address to an external address space
Translating external addresses to the local 36-bit address space
Address Translation and Mapping
Register
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Section 4.4.3.4, “Boot ROM
High-order address bits defining location of the window in the target address space
High-order address bits defining location of the window in the initial address space
Window enable, window size, target interface, and transaction attributes
Table 2-3. Format of ATMU Window Definitions
Location”). However, note that the e500 core only
Function
Table 2-3
summarizes the general
Neither is it
Memory Map
2-3