CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 8

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
tation and is exposed through GPIO pins. Refer to the BIOS
documentation for additional details on this interface.
I
I
Table 8. I
Serial Peripheral Interface
EZ-Host provides a SPI interface for added connectivity.
EZ-Host may be configured as either an SPI master or SPI
slave. The SPI interface can be exposed through GPIO pins
or the External Memory port.
SPI Features
SPI Pins
The SPI port has a few different pin location options as shown
in
Register [0xC006].
Table 9. SPI Interface Pins
2
2
• Supports EEPROMs up to 64KB (512K bit)
• Auto-detection of EEPROM size
• Master or slave mode operation
• DMA block transfer and PIO byte transfer modes
• Full duplex or half duplex data communication
• 8-byte receive FIFO and 8-byte transmit FIFO
• Selectable master SPI clock rates from 250 kHz to 12 MHz
• Selectable master SPI clock phase and polarity
• Slave SPI signaling synchronization and filtering
• Slave SPI clock rates up to 2 MHz
• Maskable interrupts for block and byte transfer modes
• Individual bit transfer for non-byte aligned serial communi-
• Programmable delay timing for the active/inactive master
• Auto or manual control for master mode slave select signal
• Complete access to internal memory
C EEPROM Features
C EEPROM Pins.
Table
cation in PIO mode
SPI clock
Pin Name
Default Location
SCK
SDA
SCK
SDA
9. The port location is selectable via the GPIO Control
Pin Name
2
C EEPROM Interface Pins
MOSI
MISO
nSSI
SCK
SMALL EEPROM
LARGE EEPROM
Pin Number
39
40
40
39
Pin Number
56 or 65
GPIO Number
61
60
66
GPIO31
GPIO30
GPIO30
GPIO31
Table 9. SPI Interface Pins (continued)
High-Speed Serial Interface
EZ-Host provides an HSS interface. The HSS interface is a
programmable serial connection with baud rate from 9600
baud to 2.0 Mbaud. The HSS interface supports both byte and
block mode operations as well as hardware and software
handshaking. Complete control of EZ-Host can be accom-
plished through this interface via an extensible API and
communication protocol. The HSS interface can be exposed
through GPIO pins or the External Memory port.
HSS Features
HSS Pins
The HSS port has a few different pin location options as shown
in
trol Register [0xC006].
Table 10.HSS Interface Pins
• 8 bits, no parity code
• Programmable baud rate from 9600 baud to 2 Mbaud
• Selectable 1- or 2-stop bit on transmit
• Programmable inter-character gap timing for Block
• 8-byte receive FIFO
• Glitch filter on receive
• Block mode transfer directly to/from EZ-Host internal
• Selectable CTS/RTS hardware signal handshake protocol
• Selectable XON/XOFF software handshake protocol
• Programmable Receive interrupt, Block Transfer Done
• Complete access to internal memory
Table
Transmit
memory (DMA transfer)
interrupts
Alternate Location
Alternate Location
Default Location
10. The port location is selectable via the GPIO Con-
Pin Name
Pin Name
MOSI
MISO
nSSI
SCK
RXD
RXD
CTS
RTS
TXD
CTS
RTS
TXD
Pin Number
Pin Number
CY7C67300
73
72
71
74
44
53
54
55
67
68
69
70
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