CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 68

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
Receive Bit Length (Bits [2:0])
The Receive Bit Length field controls whether a full byte or
partial byte will be received. If Receive Bit Length is ‘000’ then
SPI Interrupt Enable Register [0xC0CC] [R/W]
Register Description
The SPI Interrupt Enable Register controls the SPI port.
Receive Interrupt Enable (Bit 2)
The Receive Interrupt Enable bit enables or disables the byte
mode receive interrupt (RxIntVal).
1: Enable byte mode receive interrupt
0: Disable byte mode receive interrupt
Transmit Interrupt Enable (Bit 1)
The Transmit Interrupt Enable bit enables or disables the byte
mode transmit interrupt (TxIntVal).
SPI Status Register [0xC0CE] [R]
Register Description
The SPI Status Register is a read-only register that provides
status for the SPI port.
FIFO Error Flag (Bit 7)
The FIFO Error Flag bit is a read-only bit that indicates if a
FIFO error occurred. When this bit is set to ‘1’ and the Transmit
Empty bit of the SPI Control Register is set to ‘1’, then a Tx
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
FIFO Error
Flag
15
15
R
0
7
0
0
7
0
-
-
-
14
14
0
6
0
0
6
0
-
-
-
-
Figure 73. SPI Interrupt Enable Register
...Reserved
Figure 74. SPI Status Register
13
13
0
5
0
0
5
0
-
-
-
-
Reserved
12
12
0
4
0
0
4
0
-
-
-
-
Reserved...
a full byte will be received. If Receive Bit Length is ‘001’ to
‘111’, then the value indicates the number of bits that will be
received.
1: Enables byte mode transmit interrupt
0: Disables byte mode transmit interrupt
Transfer Interrupt Enable (Bit 0)
The Transfer Interrupt Enable bit enables or disables the block
mode interrupt (XfrBlkIntVal).
1: Enables block mode interrupt
0: Disables block mode interrupt
Reserved
All reserved bits should be written as ‘0’.
FIFO underflow has occurred. Similarly, when set with the
Receive Full bit of the SPI Control Register, an Rx FIFO
overflow has occured.This bit automatically clears when the
SPI FIFO Init Enable bit of the SPI Control register is set.
1: Indicates FIFO error
0: Indicates no FIFO error
Reserved
11
11
0
3
0
0
3
0
-
-
-
-
Interrupt
Interrupt
Receive
Receive
Enable
R/W
Flag
10
10
R
0
2
0
0
2
0
-
-
Transmit
Transmit
Interrupt
Interrupt
Enable
Flag
R/W
R
9
0
1
0
9
0
1
0
-
-
CY7C67300
Page 68 of 98
Interrupt
Transfer
Interrupt
Transfer
Enable
Flag
R/W
R
8
0
0
0
8
0
0
0
-
-
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