CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 13

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
Standalone Mode
In standalone mode, there is no external processor connected
to EZ-Host. Instead, EZ-Host’s own internal 16-bit CPU is the
main processor and firmware is typically downloaded from an
EEPROM. Optionally, firmware may also be downloaded via
USB. See
After booting into standalone mode (GPIO[31:30] = ‘11’), the
following pins are affected:
Minimum Hardware Requirements for Standalone Mode – Peripheral Only
Power-Savings and Reset Description
Power-Saving Mode Description
EZ-Host has one main power-saving mode, Sleep. For
detailed information on Sleep mode, see the
below.
Sleep mode is used for USB applications to support USB
suspend and non USB applications as the main chip power
down mode.
In addition, EZ-Host is capable of slowing down the CPU clock
speed through the CPU Speed Register [0xC008] without
affecting other peripheral timing. Reducing the CPU clock
speed from 48 MHz to 24 MHz reduces the overall current
draw by around 8 mA while reducing it from 48 MHz to 3 MHz
reduces the overall current draw by approximately 15 mA.
Sleep
Sleep mode is the main chip power down mode and is also
used for USB suspend. Sleep mode is entered by setting the
• GPIO[31:30] are configured as output pins to examine the
EEPROM contents
Table 19
for booting into standalone mode.
Figure 9. Minimum Standalone Hardware Configuration – Peripheral Only
*Bootloading begins after POR + 3ms BIOS bootup
*GPIO[31:30]
Up to 2k x8
>2k x8 to 64k x8
GND
Standard-B
or Mini-B
A0
A1
A2
Up to 64k x8
EEPROM
SCL SDA
SDA SCL
31
SHIELD
VBus
D+
D-
GND
30
VCC
WP
SCL
SDA
VCC
Sleep
Vcc
10k
Bootstrap Options
Vcc
VReg
10k
Bootloading Firmware
section
GPIO[30]
GPIO[31]
Reserved
VCC, AVCC,
BoostVCC
DPlus
DMinus
SCL*
SDA*
GND, AGND,
BoostGND
Sleep Enable (bit 1) of the Power Control Register [0xC00A].
During Sleep mode (USB Suspend) the following events and
states are true:
• GPIO[28:27] are enabled for debug UART mode
• GPIO[29] is configured for as OTGID for OTG applications
• Ports 1B, 2A, and 2B default as USB peripheral ports
• All other pins remain INPUT pins.
• GPIO pins maintain their configuration during sleep (in
• External Memory Address pins are driven low
• XTALOUT is turned off
• Internal PLL is turned off
• Firmware should disable the charge pump (OTG Control
• Booster circuit is turned off
• USB transceivers is turned off
• CPU goes into suspend mode until a programmable wakeup
CY7C67300
on PORT1A
— If OTGID is logic 1 then PORT1A (OTG) is configured
— If OTGID is logic 0 then PORT1A (OTG) is configured
suspend)
Register [0xC098]) causing OTGVBUS to drop below 0.2V.
Otherwise OTGVBUS only drops to V
drops).
event.
EZ-Host
Code / Data
g
Int. 16k x8
as a USB peripheral
as a USB host
nRESET
XOUT
Pin 38
XIN
* Parallel Resonant
Fundamental Mode
500uW
20-33pf ±5%
VCC
12MHz
47Kohm
Reset
Logic
p
22pf
22pf
y
CC
CY7C67300
– (2 schottky diode
Page 13 of 98
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