CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 51

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
GPIO n Output Data Register [R/W]
Register Description
The GPIO n Output Data Register controls the output data of the GPIO pins. The GPIO 0 Output Data Register controls GPIO15
to GPIO0 while the GPIO 1 Output Data Register controls GPIO31 to GPIO16. When read, this register reads back the last data
written, not the data on pins configured as inputs (see Input Data Register).
Data (Bits [15:0])
The Data field[15:0] writes to the corresponding GPIO 15–0 or GPIO31–16 pins as output data.
GPIO n Input Data Register [R]
Register Description
The GPIO n Input Data Register reads the input data of the GPIO pins. The GPIO 0 Input Data Register reads from GPIO15 to
GPIO0 while the GPIO 1 Input Data Register reads from GPIO31 to GPIO16.
Data (Bits [15:0])
The Data field[15:0] contains the voltage values on the corresponding GPIO15–0 or GPIO31–16 input pins.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• GPIO 0 Output Data Register 0xC01E
• GPIO 1 Output Data Register 0xC024
• GPIO 0 Input Data Register 0xC020
• GPIO 1 Input Data Register 0xC026
31/15
31/15
R/W
23/7
R/W
23/7
R
R
0
0
0
0
30/14
30/14
R/W
22/6
R/W
22/6
0
R
R
0
0
0
Figure 51. GPIO n Output Data Register
Figure 52. GPIO n Input Data Register
29/13
29/13
21//5
21/5
R/W
R/W
0
R
R
0
0
0
28/12
28/12
20/4
R/W
R/W
20/4
0
0
R
R
0
0
Data...
...Data
Data...
...Data
27/11
27/11
19/3
R/W
R/W
19/3
0
0
R
R
0
0
26/10
26/10
18/2
R/W
R/W
18/2
0
0
R
R
0
0
25/9
R/W
17/1
R/W
25/9
17/1
0
0
R
R
0
0
CY7C67300
Page 51 of 98
16/0
R/W
24/8
R/W
24/8
16/0
0
0
R
R
0
0
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