CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 57

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
Transmit Ready (Bit 4)
The Transmit Ready bit is a read-only bit that indicates if the
HSS Transmit FIFO is ready for the CPU to load new data for
transmission.
1: HSS transmit FIFO ready for loading
0: HSS transmit FIFO not ready for loading
Packet Mode Select (Bit 3)
The Packet Mode Select bit selects between Receive Packet
Ready and Receive Ready as the interrupt source for the
RxIntr interrupt.
1: Selects Receive Packet Ready as the source
0: Selects Receive Ready as the source
Receive Overflow Flag (Bit 2)
The Receive Overflow Flag bit indicates if the Receive FIFO
overflowed when set. This flag can be cleared by writing a ‘1’
to this bit.
HSS Baud Rate Register [0xC072] [R/W]
Register Description
The HSS Baud Rate Register sets the HSS Baud Rate. At reset, the default value is 0x0017 which sets the baud rate to 2.0 MHz.
Baud (Bits [12:0])
The Baud field is the baud rate divisor minus one, in units of 1/48 MHz. Therefore the Baud Rate = 48 MHz/(Baud + 1). This puts
a constraint on the Baud Value as follows: (24 – 1) ≤ Baud ≥ (5000 – 1)
Reserved
All reserved bits should be written as ‘0’.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
R/W
15
0
7
0
-
Reserved
R/W
14
0
6
0
-
Figure 59. HSS Baud Rate Register
R/W
13
0
5
0
-
R/W
R/W
12
0
4
1
1: Overflow occurred
0: Overflow did not occur
Receive Packet Ready Flag (Bit 1)
The Receive Packet Ready Flag bit is a read-only bit that
indicates if the HSS receive FIFO is full with eight bytes or not.
1: HSS receive FIFO is full
0: HSS receive FIFO is not full
Receive Ready Flag (Bit 0)
The Receive Ready Flag is a read-only bit that indicates if the
HSS receive FIFO is empty or not.
1: HSS receive FIFO is not empty (one or more bytes is
reading for reading)
0: HSS receive FIFO is empty
...Baud
R/W
R/W
11
0
3
0
Baud...
R/W
R/W
10
0
2
1
R/W
R/W
9
0
1
1
CY7C67300
Page 57 of 98
R/W
R/W
8
0
0
1
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