CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 54

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
Register Description
The IDE Stop Address Register holds the stop address for an IDE block transfer. This register is byte addressed and IDE block
transfers are 16-bit words, therefore the LSB of the stop address is ignored. Block transfers begin at IDE Start Address and end
with the final word at IDE Stop Address. When IDE Start Address equals IDE Stop Address, the block transfer moves one word
of data.
The hardware keeps an internal memory address counter. The two MSBs of the addresses are not modified by the address
counter. Therefore the IDE Start Address and IDE Stop Address must reside within the same 16-Kbyte block.
Address (Bits [15:0])
The Address field sets the stop address for an IDE block transfer.
IDE Control Register [0xC04E] [R/W]
Register Description
The IDE Control Register controls block transfers in IDE mode.
Direction Select (Bit 3)
The Direction Select bit sets the block mode transfer direction.
1: Data is written to the external device
0: Data is read from the external device
IDE Interrupt Enable (Bit 2)
The IDE Interrupt Enable bit enables or disables the block
transfer done interrupt. When enabled, the Done Flag is sent
to the CPU as cpuide_intr interrupt. When disabled, the
cpuide_intr is set LOW.
1: Enable block transfer done interrupt
0: Disable block transfer done interrupt
Done Flag (Bit 1)
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
15
0
7
0
-
-
14
0
6
0
-
-
...Reserved
Figure 57. IDE Control Register
13
0
5
0
-
-
12
0
4
0
-
-
Reserved...
The Done Flag bit is automatically set to ‘1’ by hardware when
a block transfer is complete. The CPU clears this bit by writing
a ‘0’ to it. When IDE Interrupt Enable is set this bit generates
the signal for the cpuide_intr interrupt.
1: Block transfer is complete
0: Clears IDE Done Flag
IDE Enable (Bit 0)
The IDE Enable bit will start a block transfer. It is reset to ‘0’
when the block transfer is complete
1: Start block transfer
0: Block transfer complete
Reserved
All reserved bits should be written as ‘0’.
Direction
Select
R/W
11
0
3
0
-
Interrupt
Enable
R/W
IDE
10
0
2
0
-
Done
Flag
R/W
9
0
1
0
-
CY7C67300
Page 54 of 98
Enable
R/W
IDE
8
0
0
0
-
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