CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 45

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also
be set so that NAK responses trigger this interrupt.
1: Enable EP1 Transaction Done interrupt
0: Disable EP1 Transaction Done interrupt
EP0 Interrupt Enable (Bit 0)
The EP0 Interrupt Enable bit enables or disables endpoint
zero (EP0) Transaction Done interrupt. An EPx Transaction
Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given Endpoint:
Device n Address Register [W]
Register Description
The Device n Address Register holds the device address
assigned by the host. This register initializes to the default
address 0 at reset but must be updated by firmware when the
host assigns a new address. Only USB data sent to the
address contained in this register will be responded to—all
others are ignored.
Device n Status Register [R/W]
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Device 1 Address Register 0xC08E
• Device 2 Address Register 0xC0AE
• Device 1 Status Register 0xC090
• Device 2 Status Register 0xC0B0
EP7 Interrupt
VBUS Inter-
...Reserved
Flag
R/W
Flag
R/W
rupt
15
15
X
X
0
7
0
7
-
-
EP6 Interrupt
ID Interrupt
Flag
R/W
Flag
R/W
14
14
W
X
X
0
6
0
6
-
Figure 45. Device n Address Register
EP5 Interrupt
Figure 46. Device n Status Register
Flag
R/W
13
13
W
X
X
0
5
0
5
-
-
EP4 Interrupt
Flag
R/W
12
12
W
X
0
4
0
X
4
-
-
Reserved...
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also
be set so that NAK responses trigger this interrupt.
1: Enable EP0 Transaction Done interrupt
0: Disable EP0 Transaction Done interrupt
Reserved
All reserved bits should be written as ‘0’.
Address (Bits [6:0])
The Address field contains the USB address of the device
assigned by the host.
Reserved
All reserved bits should be written as ‘0’.
Reserved
EP3 Interrupt
Address
Flag
R/W
11
11
W
X
0
3
0
X
3
-
-
EP2 Interrupt
Flag
R/W
10
10
W
X
0
2
0
X
2
-
-
Interrupt Flag
EP1 Interrupt
SOF/EOP
Flag
R/W
R/W
W
X
9
0
1
0
9
X
1
-
CY7C67300
Page 45 of 98
Reset Interrupt
EP0 Interrupt
Flag
R/W
Flag
R/W
W
X
8
0
X
0
-
0
0
8
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