CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 33

IC,Peripheral (Multifunction) Controller,QFP,100PIN

CY7C67300-100AXA

Manufacturer Part Number
CY7C67300-100AXA
Description
IC,Peripheral (Multifunction) Controller,QFP,100PIN
Manufacturer
Cypress Semiconductor Corp
Series
EZ-Host™r
Datasheet

Specifications of CY7C67300-100AXA

Applications
USB Host/Peripheral Controller
Core Processor
CY16
Program Memory Type
ROM (8 kB)
Controller Series
CY7C673xx
Ram Size
16K x 8
Interface
SPI Serial, USB, HPI
Number Of I /o
32
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C67300-100AXA
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C67300-100AXAT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-08015 Rev. *G
PID Select (Bits [7:4])
The PID Select field is defined in
tokens are automatically sent based on settings in the Host n
Control Register and do not need to be written in this register.
Table 34.PID Select Definition
Host n Count Result Register [R]
Register Description
The Host n Count Result Register is a read-only register that
contains the size difference in bytes between the Host Count
Value specified in the Host n Count Register and the last
packet received. If an overflow or underflow condition occurs,
that is the received packet length differs from the value
specified in the Host n Count Register, the Length Exception
Flag bit in the Host n Endpoint Status Register will be set. The
value in this register is only value when the Length Exception
Flag bit is set and the Error Flag bit is not set, both bits are in
the Host n Endpoint Status Register.
SETUP
IN
OUT
SOF
PREAMBLE
NAK
STALL
DATA0
DATA1
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Host 1 Count Result Register 0xC088.
• Host 2 Count Result Register 0xC0A8.
PID TYPE
15
R
R
0
7
0
14
R
R
0
6
0
Table
PID Select [7:4]
1101 (D Hex)
1100 (C Hex)
1010 (A Hex)
1011 (B Hex)
1001 (9 Hex)
0001 (1 Hex)
0101 (5 Hex)
1110 (E Hex)
0011 (3 Hex)
34. ACK and NAK
Figure 31. Host n Count Result Register
13
R
R
0
5
0
12
R
R
0
4
0
Endpoint Select (Bits [3:0])
The Endpoint field allows addressing of up to 16 different
endpoints.
Reserved
All reserved bits should be written as ‘0’.
Result (Bits [15:0])
The Result field contains the differences in bytes between the
received packet and the value specified in the Host n Count
Register. If an overflow condition occurs, Result [15:10] will be
set to ‘111111’, a 2’s complement value indicating the
additional byte count of the received packet. If an underflow
condition occurs, Result [15:0] indicates the excess bytes
count (number of bytes not used).
Reserved
All reserved bits should be written as ‘0’.
Result...
...Result
11
R
R
0
3
0
10
R
R
0
2
0
R
R
9
0
1
0
CY7C67300
Page 33 of 98
R
R
8
0
0
0
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