CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 58

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
HSS Transmit Gap Register [0xC074] [R/W]
Register Description
The HSS Transmit Gap Register is only valid in block transmit mode. It allows for a programmable number of stop bits to be
inserted, thus overwriting the One Stop Bit in the HSS Control Register. The default reset value of this register is 0x0009,
equivalent to two stop bits.
Transmit Gap Select (Bits [7:0])
The Transmit Gap Select field sets the inactive time between transmitted bytes. The inactive time = (Transmit Gap Select – 7) *
bit time. Therefore an Transmit Gap Select Value of 8 is equal to having one Stop bit.
Reserved
All reserved bits should be written as ‘0’.
HSS Data Register [0xC076] [R/W]
Register Description
The HSS Data Register contains data received on the HSS port (not for block receive mode) when read. This receive data is valid
when the Receive Ready bit of the HSS Control Register is set to ‘1’. Writing to this register initiates a single byte transfer of data.
The Transmit Ready Flag in the HSS Control Register should read ‘1’ before writing to this register (this avoids disrupting the
previous/current transmission).
Data (Bits [7:0])
The Data field contains the data received or to be transmitted on the HSS port.
Reserved
All reserved bits should be written as ‘0’.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
R/W
R/W
15
15
X
X
0
7
0
7
-
-
R/W
R/W
14
14
X
X
0
6
0
6
-
-
Figure 60. HSS Transmit Gap Register
R/W
R/W
Figure 61. HSS Data Register
13
13
X
X
0
5
0
5
-
-
Transmit Gap Select
R/W
R/W
12
12
0
X
X
4
0
4
-
-
Reserved
Reserved
Data
R/W
R/W
11
11
0
X
X
3
1
3
-
-
R/W
R/W
10
10
0
X
X
2
0
2
-
-
R/W
R/W
9
0
X
X
-
1
0
9
1
-
CY7C67300
Page 58 of 98
R/W
R/W
8
0
X
X
-
0
1
8
0
-
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