CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 28

IC,Peripheral (Multifunction) Controller,QFP,100PIN

CY7C67300-100AXA

Manufacturer Part Number
CY7C67300-100AXA
Description
IC,Peripheral (Multifunction) Controller,QFP,100PIN
Manufacturer
Cypress Semiconductor Corp
Series
EZ-Host™r
Datasheet

Specifications of CY7C67300-100AXA

Applications
USB Host/Peripheral Controller
Core Processor
CY16
Program Memory Type
ROM (8 kB)
Controller Series
CY7C673xx
Ram Size
16K x 8
Interface
SPI Serial, USB, HPI
Number Of I /o
32
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C67300-100AXA
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C67300-100AXAT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-08015 Rev. *G
Port B D– Status (Bit 14)
The Port B D– Status bit is a read-only bit that indicates the
value of DATA– on Port B.
1: D– is HIGH
0: D– is LOW
Port A D+ Status (Bit 13)
The Port A D+ Status bit is a read-only bit that indicates the
value of DATA+ on Port A.
1: D+ is HIGH
0: D+ is LOW
Port A D– Status (Bit 12)
The Port A D– Status bit is a read-only bit that indicates the
value of DATA– on Port A.
1: D– is HIGH
0: D– is LOW
LOB (Bit 11)
The LOB bit selects the speed of Port B.
1: Port B is set to low-speed mode
0: Port B is set to full-speed mode
LOA (Bit 10)
The LOA bit selects the speed of Port A.
1: Port A is set to low-speed mode
0: Port A is set to full-speed mode
Mode Select (Bit 9)
The Mode Select bit sets the SIE for host or device operation.
When set for device operation only one USB port is supported.
The active port is selected by the Port Select bit in the Host n
Count Register.
1: Host mode
0: Device mode
Port B Resistors Enable (Bit 8)
The Port B Resistors Enable bit enables or disables the pull-
up/pull-down resistors on Port B. When enabled, the Mode
Select bit and LOB bit of this Register set the pull-up/pull-down
resistors appropriately. When the Mode Select is set for Host
mode, the pull-down resistors on the data lines (D+ and D–)
are enabled. When the Mode Select is set for Device mode, a
single pull-up resistor on either D+ or D–, determined by the
LOB bit, will be enabled. See
1: Enable pull-up/pull-down resistors
0: Disable pull-up/pull-down resistors
Port A Resistors Enable (Bit 7)
The Port A Resistors Enable bit enables or disables the
pull-up/pull-down resistors on Port A. When enabled, the
Mode Select bit and LOA bit of this Register set the
pull-up/pull-down resistors appropriately. When the Mode
Select is set for Host mode, the pull-down resistors on the data
lines (D+ and D–) are enabled. When the Mode Select is set
Table 30
for details.
for Device mode, a single pull-up resistor on either D+ or D–,
determined by the LOA bit, will be enabled. See
details.
1: Enable pull-up/pull-down resistors
0: Disable pull-up/pull-down resistors
Table 30.USB Data Line Pull-up and Pull-down Resistors
Port B Force D± State (Bits [6:5])
The Port B Force D± State field controls the forcing state of the
D+ D– data lines for Port B. This field forces the state of the
Port B data lines independent of the Port Select bit setting. See
Table 31
Port A Force D± State (Bits [4:3])
The Port A Force D± State field controls the forcing state of the
D+ D– data lines for Port A. This field forces the state of the
Port A data lines independent of the Port Select bit setting. See
Table 31
Table 31.Port A/B Force D± State
Suspend Enable (Bit 2)
The Suspend Enable bit enables or disables the suspend
feature on both ports. When suspend is enabled the USB
transceivers are powered down and can not transmit or
received USB packets but can still monitor for a wakeup
condition.
1: Enable suspend
0: Disable suspend
Port B SOF/EOP Enable (Bit 1)
The Port B SOF/EOP Enable bit is only applicable in host
mode. In device mode this bit should be written as ‘0’. In host
mode this bit enables or disables SOFs or EOPs for Port B.
Either SOFs or EOPs will be generated depending on the LOB
bit in the USB n Control Register when Port B is active.
1: Enable SOFs or EOPs
0: Disable SOFs or EOPs
L0A/
Port A/B Force D± State
L0B
X
X
1
0
MSb
0
1
0
1
Select
for details.
for details.
Mode
X
1
0
0
Resistors
LSb
Enable
Port n
0
0
1
1
0
1
1
1
Normal Operation
Force USB Reset, SE0 State
Force J-State
Force K-State
Pull up/Pull down on D+ and
D– Disabled
Pull down on D+ and
D– Enabled
Pull up on USB D– Enabled
Pull up on USB D+ Enabled
Function
CY7C67300
Function
Page 28 of 98
Table 30
for
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