CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 23

IC,Peripheral (Multifunction) Controller,QFP,100PIN

CY7C67300-100AXA

Manufacturer Part Number
CY7C67300-100AXA
Description
IC,Peripheral (Multifunction) Controller,QFP,100PIN
Manufacturer
Cypress Semiconductor Corp
Series
EZ-Host™r
Datasheet

Specifications of CY7C67300-100AXA

Applications
USB Host/Peripheral Controller
Core Processor
CY16
Program Memory Type
ROM (8 kB)
Controller Series
CY7C673xx
Ram Size
16K x 8
Interface
SPI Serial, USB, HPI
Number Of I /o
32
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C67300-100AXA
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C67300-100AXAT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-08015 Rev. *G
Memory Diagnostic Register [0xC03E] [W]
Register Description
The Memory Diagnostic Register provides control of
diagnostic modes.
Memory Arbitration Select (Bits[10:8])
The Memory Arbitration Select field is defined in
Table 25.Memory Arbitration Select
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Memory Arbitration
Select [3:0]
101
100
010
001
000
111
110
011
15
0
7
0
-
-
Memory Arbitration Timing
1/8, 7 of every 8 cycles dead
2/8, 6 of every 8 cycles dead
3/8, 5 of every 8 cycles dead
4/8, 4 of every 8 cycles dead
5/8, 3 of every 8 cycles dead
6/8, 2 of every 8 cycles dead
7/8, 1 of every 8 cycles dead
8/8, all cycles available
14
0
6
0
-
-
Figure 19. Memory Diagnostic Register
Reserved
13
Table
0
5
0
-
-
25.
Reserved
12
0
4
0
-
-
Monitor Enable (Bit 0)
The Monitor Enable bit enables or disables monitor mode. In
monitor mode the internal address bus is echoed to the
external address pins.
1: Enable monitor mode
0: Disable monitor mode
Reserved
All reserved bits should be written as ‘0’.
External Memory Registers
There are four registers dedicated to controlling the external
memory interface. Each of these registers are covered in this
section and are summarized in
Table 26.External Memory Control Registers
Extended Page 1 Map Register
Extended Page 2 Map Register
Upper Address Enable Register
External Memory Control Register
11
0
3
0
Register Name
-
-
10
W
0
2
0
-
Table 26
Arbitration
Memory
Select
0xC018
0xC01A
0xC038
0xC03A
W
9
0
1
0
-
CY7C67300
Address
Page 23 of 98
Monitor
Enable
R/W
R/W
R/W
R/W
W
W
8
0
0
0
R/W
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