CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 60

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
HSS Transmit Address Register [0xC07C] [R/W]
Register Description
The HSS Transmit Address Register is used as the base pointer address for the next HSS block transmit transfer.
Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS block transmit transfer.
HSS Transmit Counter Register [0xC07E] [R/W]
Register Description
The HSS Transmit Counter Register designates the block byte length for the next HSS transmit transfer. This register should be
loaded with the word count minus one to start the block transmit transfer. As each byte is transmitted this register value is
decremented. When read, this register indicates the remaining length of the transfer.
Counter (Bits [9:0])
The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When
the transfer is complete this register returns 0x03FF until reloaded.
Reserved
All reserved bits should be written as ‘0’.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
R/W
R/W
R/W
15
15
0
7
0
0
7
0
-
R/W
R/W
R/W
14
14
0
6
0
0
6
0
-
Figure 64. HSS Transmit Address Register
Figure 65. HSS Transmit Counter Register
R/W
R/W
R/W
13
13
0
5
0
0
5
0
-
Reserved
R/W
R/W
R/W
12
12
0
4
0
0
4
0
-
Address...
...Address
...Counter
R/W
R/W
R/W
11
11
0
3
0
0
3
0
-
R/W
R/W
R/W
10
10
0
2
0
0
2
0
-
R/W
R/W
R/W
R/W
9
0
1
0
9
0
1
0
CY7C67300
Counter...
Page 60 of 98
R/W
R/W
R/W
R/W
8
0
0
0
8
0
0
0
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