CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 34

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
Host n Device Address Register [W]
Register Description
The Host n Device Address Register is a write-only register
that contains the USB Device Address that the host wishes to
communicate with.
Host n Interrupt Enable Register [R/W]
Register Description
The Host n Interrupt Enable Register allows control over host
related interrupts.
In this register a bit set to ‘1’ enables the corresponding
interrupt while ‘0’ disables the interrupt.
VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit enables or disables the OTG
VBUS interrupt. When enabled this interrupt triggers on both
the rising and falling edge of VBUS at the 4.4V status (only
supported in Port 1A). This bit is only available for Host 1 and
is a reserved bit in Host 2.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Host 1 Device Address Register 0xC088.
• Host 2 Device Address Register 0xC0A8.
• Host 1 Interrupt Enable Register 0xC08C.
• Host 2 Interrupt Enable Register 0xC0AC.
Wake Interrupt
...Reserved
Interrupt
Enable
Enable
VBUS
Port B
R/W
R/W
15
15
0
7
0
0
7
0
-
-
Wake Interrupt
ID Interrupt
Enable
Enable
Port A
R/W
R/W
14
W
14
0
6
0
-
0
6
0
Figure 32. Host n Device Address Register
Figure 33. Host n Interrupt Enable Register
Port B Connect
Interrupt
Change
Enable
13
R/W
W
13
0
5
0
-
0
-
5
0
Port A Connect
Interrupt
Change
Enable
12
W
12
4
0
0
R/W
-
0
-
4
0
Reserved...
Address (Bits [6:0])
The Address field contains the value of the USB address for
the next device that the host is going to communicate with.
This value must be written by firmware.
Reserved
All reserved bits should bit written as ‘0’.
1: Enable VBUS interrupt
0: Disable VBUS interrupt
ID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit enables or disables the OTG ID
interrupt. When enabled this interrupt triggers on both the
rising and falling edge of the OTG ID pin (only supported in
Port 1A). This bit is only available for Host 1 and is a reserved
bit in Host 2.
1: Enable ID interrupt
0: Disable ID interrupt
Reserved
Address
11
W
11
3
0
0
-
0
-
3
0
-
Reserved
10
W
10
2
0
2
0
0
-
-
0
-
SOF/EOP
Interrupt
Enable
R/W
W
1
0
1
0
9
0
-
9
0
-
CY7C67300
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Reserved
Interrupt
Enable
Done
R/W
W
0
0
0
0
8
0
-
8
0
-
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