CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 64

IC,Peripheral (Multifunction) Controller,QFP,100PIN

CY7C67300-100AXA

Manufacturer Part Number
CY7C67300-100AXA
Description
IC,Peripheral (Multifunction) Controller,QFP,100PIN
Manufacturer
Cypress Semiconductor Corp
Series
EZ-Host™r
Datasheet

Specifications of CY7C67300-100AXA

Applications
USB Host/Peripheral Controller
Core Processor
CY16
Program Memory Type
ROM (8 kB)
Controller Series
CY7C673xx
Ram Size
16K x 8
Interface
SPI Serial, USB, HPI
Number Of I /o
32
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C67300-100AXA
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C67300-100AXAT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-08015 Rev. *G
HPI Status Port [] [HPI: R]
Register Description
The HPI Status Port provides the external host processor with
the MailBox status bits plus several SIE status bits. This
register is not accessible from the onchip CPU. The additional
SIE status bits are provided to aid external device driver
firmware development, and are not recommended for applica-
tions that do not have an intimate relationship with the onchip
BIOS.
Reading from the HPI Status Port does not result in a CPU HPI
interface memory access cycle. The external host may contin-
uously poll this register without degrading the CPU or DMA
performance.
VBUS Flag (Bit 15)
The VBUS Flag bit is a read-only bit that indicates whether
OTG VBus is greater than 4.4V. After turning on VBUS,
firmware should wait at least 10 µs before this reading this bit.
1: OTG VBus is greater than 4.4V
0: OTG VBus is less than 4.4V
ID Flag (Bit 14)
The ID Flag bit is a read-only bit that indicates the state of the
OTG ID pin.
SOF/EOP2 Flag (Bit 12)
The SOF/EOP2 Flag bit is a read-only bit that indicates if a
SOF/EOP interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
SOF/EOP1 Flag (Bit 10)
The SOF/EOP1 Flag bit is a read-only bit that indicates if a
SOF/EOP interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
Reset2 Flag (Bit 9)
The Reset2 Flag bit is a read-only bit that indicates if a USB
Reset interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Resume2
VBUS
Flag
Flag
15
R
X
R
X
7
Resume1
Flag
Flag
14
ID
R
X
R
X
6
Reserved
SIE2msg
13
X
R
X
5
-
Figure 70. HPI Status Port
SOF/EOP2
SIE1msg
Flag
12
R
X
R
X
4
Mailbox In Flag (Bit 8)
The Mailbox In Flag bit is a read-only bit that indicates if a
message is ready in the incoming mailbox. This interrupt
clears when the onchip CPU reads from the HPI Mailbox
Register.
1: Interrupt triggered
0: Interrupt did not trigger
Resume2 Flag (Bit 7)
The Resume2 Flag bit is a read-only bit that indicates if a USB
resume interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
Resume1 Flag (Bit 6)
The Resume1 Flag bit is a read-only bit that indicates if a USB
resume interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
SIE2msg (Bit 5)
The SIE2msg Flag bit is a read only bit that indicates if the
CY7C67300 CPU has written to the SIE2msg register. This bit
is cleared on an HPI read.
1: The SIE2msg register has been written by the CY7C67300
CPU
0: The SIE2msg register has not been written by the
CY7C67300 CPU
SIE1msg (Bit 4)
The SIE1msg Flag bit is a read only bit that indicates if the
CY7C67300 CPU has written to the SIE1msg register. This bit
is cleared on an HPI read.
1: The SIE1msg register has been written by the CY7C67300
CPU
0: The SIE1msg register has not been written by the
CY7C67300 CPU
Done2 Flag (Bit 3)
In host mode the Done2 Flag bit is a read-only bit that indicates
if a host packet done interrupt occurs on Host 2. In device
Reserved
Done2
Flag
11
X
R
X
3
-
SOF/EOP1
Done1
Flag
Flag
10
R
X
R
X
2
Reset2
Reset1
Flag
Flag
R
X
R
X
9
1
CY7C67300
Page 64 of 98
Mailbox Out
Mailbox In
Flag
Flag
R
X
R
X
8
0
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