CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 47

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control Register is set, this
interrupt also triggers when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP0 Interrupt Flag (Bit 0)
The EP0 Interrupt Flag bit indicates if the endpoint zero (EP0)
Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt triggers when any of the following responses or
Device n Frame Number Register [R]
Register Description
The Device n Frame Number Register is a read-only register
that contains the Frame number of the last SOF packet
received. This register also contains a count of SOF/EOP
Timeout occurrences.
SOF/EOP Timeout Flag (Bit 15)
The SOF/EOP Timeout Flag bit indicates when an SOF/EOP
Timeout Interrupt occurs.
1: An SOF/EOP Timeout interrupt occurred
0: An SOF/EOP Timeout interrupt did not occur
Device n SOF/EOP Count Register [W]
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Device 1 Frame Number Register 0xC092
• Device 2 Frame Number Register 0xC0B2
• Device 1 SOF/EOP Count Register 0xC094
• Device 2 SOF/EOP Count Register 0xC0B4
Timeout Flag
SOF/EOP
15
15
R
R
R
0
7
0
0
7
1
-
Reserved
14
14
R
0
R
R
6
0
0
6
1
-
Timeout Interrupt Counter
Figure 48. Device n SOF/EOP Count Register
Figure 47. Device n Frame Number Register
SOF/EOP
13
13
R
R
R
0
R
5
0
1
5
1
12
12
R
R
R
0
4
0
R
4
0
0
events occur in a transaction for the device’s given EP:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control Register is set, this
interrupt also triggers when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
Reserved
All reserved bits should be written as ‘0’.
SOF/EOP Timeout Interrupt Counter (Bits [14:12])
The SOF/EOP Timeout Interrupt Counter field increments by
1 from 0 to 7 for each SOF/EOP Timeout Interrupt. This field
resets to 0 when a SOF/EOP is received. This field is only
updated when the SOF/EOP Timeout Interrupt Enable bit in
the Device n Interrupt Enable Register is set.
Frame (Bits [10:0])
The Frame field contains the frame number from the last
received SOF packet in full-speed mode. This field has no
function for low-speed mode. If a SOF Timeout occurs, this
field contains the last received Frame number.
...Frame
...Count
Reserved
11
11
R
R
0
3
0
R
3
0
-
1
Count...
10
10
R
R
R
0
2
0
R
2
0
1
Frame...
R
9
0
R
R
1
0
R
1
0
9
1
CY7C67300
Page 47 of 98
R
8
0
R
R
0
0
0
0
R
8
0
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