CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 29

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
Port A SOF/EOP Enable (Bit 0)
The Port A SOF/EOP Enable bit is only applicable in host
mode. In device mode this bit should be written as ‘0’. In host
mode this bit enables or disables SOFs or EOPs for Port A.
Either SOFs or EOPs will be generated depending on the LOA
bit in the USB n Control Register when Port A is active.
1: Enable SOFs or EOPs
0: Disable SOFs or EOPs
USB Host Only Registers
There are twelve sets of dedicated registers for USB host only operation. Each set consists of two identical registers (unless
otherwise noted), one for Host Port 1 and one for Host Port 2. These register sets are covered in this section and summarized
in
Table 32.USB Host Only Register
Host n Control Register [R/W]
Register Description
The Host n Control Register allows high-level USB transaction
control.
Host n Control Register
Host n Address Register
Host n Count Register
Host n Endpoint Status Register
Host n PID Register
Host n Count Result Register
Host n Device Address Register
Host n Interrupt Enable Register
Host n Status Register
Host n SOF/EOP Count Register
Host n SOF/EOP Counter Register
Host n Frame Register
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Host 1 Control Register 0xC080.
• Host 2 Control Register 0xC0A0.
Table
32.
Preamble
Enable
R/W
15
0
7
0
-
Register Name
Sequence
Select
R/W
14
0
6
0
-
Figure 26. Host n Control Register
Enable
Sync
R/W
13
0
5
0
-
Enable
R/W
ISO
12
0
4
0
-
Reserved
All reserved bits should be written as ‘0’.
Preamble Enable (Bit 7)
The Preamble Enable bit enables or disables the transmission
of a preamble packet before all low-speed packets. This bit
should only be set when communicating with a low-speed
device.
1: Enable Preamble packet
0: Disable Preamble packet
Reserved
0xC080/0xC0A0
0xC082/0xC0A2
0xC084/0xC0A4
0xC086/0xC0A6
0xC086/0xC0A6
0xC088/0xC0A8
0xC088/0xC0A8
0xC08C/0xC0AC
0xC090/0xC0B0
0xC092/0xC0B2
0xC094/0xC0B4
0xC096/0xC0B6
Address (Host 1/Host 2)
11
0
3
0
-
-
Reserved
10
0
2
0
-
-
9
0
1
0
-
-
CY7C67300
Page 29 of 98
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
R
R
Enable
R/W
Arm
8
0
0
0
-
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