CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 10

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
IDE Interface
EZ-Host has an IDE interface. The IDE interface supports PIO
mode 0-4 as specified in the Information Technology-AT
Attachment–4 with Packet Interface Extension (ATA/ATAPI-4)
Specification, T13/1153D Rev 18. There is no need for
firmware to use programmable wait states. The CPU
read/write cycle is automatically extended as needed for direct
CPU to IDE read/write accesses.
Table 14.IDE Throughput
IDE Features
IDE Pins
Table 15.IDE Interface Pins
T = System clock period = 1/48 MHz.
• Programmable I/O mode 0–4
• Block mode transfers
• Direct memory access to/from internal memory through the
IDE Data Register
PIO Mode 0
PIO Mode 1
PIO Mode 2
PIO Mode 3
PIO Mode 4
Pin Name
Mode
IORDY
IOW
CS1
CS0
D15
D14
D13
D12
D10
IOR
D11
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A2
A1
A0
Min. Cycle Time
ATA/ATAPI-4
600 ns
383 ns
180 ns
120 ns
240
Pin Number
46
47
48
50
52
53
54
55
56
57
58
59
60
61
65
66
86
87
89
90
91
92
93
94
Min. Cycle Time
20T = 416.7 ns
13T = 270.8 ns
10T = 208.3 ns
8T = 166.7 ns
30T = 625 ns
Actual
The EZ-Host IDE interface also has a BLOCK transfer mode
that allows EZ-Host to read/write large blocks of data to/from
the IDE Data Register and move it to/from the EZ-Host onchip
memory directly without intervention of the CPU. The IDE
interface is exposed through GPIO pins.
achieved throughput for maximum block mode data transfer
rate (with IDE_IORDY true) for the various IDE PIO modes
Charge Pump Interface
VBUS for the USB OTG port can be produced by EZ-Host
using its built-in charge pump and some external components.
The circuit connections should look similar to the diagram be-
low.
Component details:
If the VBUS charge pump circuit is not to be used,
CSWITCHA, CSWITCHB, and OTGVBUS can be left uncon-
nected.
Charge Pump Features
CY7C67300
• D1 and D2: Schottky diodes with a current rating greater
• C1: Ceramic capacitor with a capacitance of 0.1 µF
• C2: Capacitor value should be no more that 6.5 µF since
• Meets OTG Supplement Requirements, see DC Character-
than 60 mA
that is the maximum capacitance allowed by the USB OTG
spec for a dual-role device. The minimum value of C2 is
1 µF. There are no restrictions on the type of capacitor for
C2.
istics: Charge Pump
CSWITCHA
CSWITCHB
OTGVBUS
Max. Transfer Rate
ATA/ATPI-4
16.67 MB/s
11.11 MB/s
3.33 MB/s
5.22 MB/s
8.33 MB/s
Figure 5. Charge Pump
D1
Table 54
C1
for details.
D2
Max. Transfer Rate
CY7C67300
C2
7.38 MB/s
12.0 MB/s
Table 14
3.2 MB/s
4.8 MB/s
9.6 MB/s
Actual
Page 10 of 98
VBUS
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