CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 43

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
Result (Bits [15:0])
The Result field contains the differences in bytes between the received packet and the value specified in the Device n Endpoint
n Count Register. If an overflow condition occurs, Result [15:10] will be set to ‘111111’, a 2’s complement value indicating the
additional byte count of the received packet. If an underflow condition occurs, Result [15:0] will indicate the excess bytes count
(number of bytes not used).
Reserved
All reserved bits should be written as ‘0’.
Device n Port Select Register [R/W]
Register Description
The Device n Port Select Register selects either port A or port B for the static device port.
Port Select (Bit 14)
The Port Select bit selects which of the two ports is enabled
1: Port 1B or Port 2B is enabled
0: Port 1A or Port 2A is enabled
Device n Interrupt Enable Register [R/W]
Register Description
The Device n Interrupt Enable Register provides control over
device-related interrupts including eight different endpoint
interrupts.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Device n Port Select Register 0xC084
• Device n Port Select Register 0xC0A4
• Device 1 Interrupt Enable Register 0xC08C
• Device 2 Interrupt Enable Register 0xC0AC
EP7 Interrupt
Reserved
Interrupt
Enable
Enable
VBUS
R/W
R/W
15
15
0
7
0
0
7
0
-
-
EP6 Interrupt
ID Interrupt
Enable
Enable
Select
R/W
R/W
R/W
Port
14
14
0
6
0
0
6
0
-
Figure 44. Device n Interrupt Enable Register
Figure 43. Device n Port Select Register
EP5 Interrupt
Enable
R/W
13
13
0
5
0
0
5
0
-
-
-
Reserved
EP4 Interrupt
Enable
R/W
12
12
4
0
0
4
0
0
-
-
-
...Reserved
VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit enables or disables the OTG
VBUS interrupt. When enabled, this interrupt triggers on both
the rising and falling edge of VBUS at the 4.4V status (only
EP3 Interrupt
SOF/EOP
Interrupt
Timeout
Enable
Enable
R/W
R/W
11
11
3
0
0
3
0
0
-
-
Reserved...
EP2 Interrupt
Reserved
Enable
R/W
10
10
2
0
0
2
0
0
-
-
-
EP1 Interrupt
SOF/EOP
Interrupt
Enable
Enable
R/W
R/W
1
0
9
0
1
0
9
0
-
-
CY7C67300
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EP0 Interrupt
Interrupt
Enable
Enable
Reset
R/W
R/W
0
0
8
0
8
0
0
0
-
-
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