CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 38

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
USB Device Only Registers
There are eleven sets of USB Device Only registers. All sets consist of at least two registers, one for Device Port 1 and one for
Device Port 2. In addition, each Device port has eight possible endpoints. This gives each endpoint register set eight registers
for each Device Port for a total of sixteen registers per set. The USB Device Only registers are covered in this section and
summarized in
Table 35.USB Device Only Registers
Device n Endpoint n Control Register [R/W]
Register Description
The Device n Endpoint n Control Register provides control
over a single EP in device mode. There are a total of eight
endpoints for each of the two ports. All endpoints have the
same definition for their Device n Endpoint n Control Register.
Register Name
Device n Endpoint n Control Register
Device n Endpoint n Address Register
Device n Endpoint n Count Register
Device n Endpoint n Status Register
Device n Endpoint n Count Result Register
Device n Port Select Register
Device n Interrupt Enable Register
Device n Address Register
Device n Status Register
Device n Frame Number Register
Device n SOF/EOP Count Register
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Device n Endpoint 0 Control Register [Device 1: 0x0200 Device 2: 0x0280]
• Device n Endpoint 1 Control Register [Device 1: 0x0210 Device 2: 0x0290]
• Device n Endpoint 2 Control Register [Device 1: 0x0220 Device 2: 0x02A0]
• Device n Endpoint 3 Control Register [Device 1: 0x0230 Device 2: 0x02B0]
• Device n Endpoint 4 Control Register [Device 1: 0x0240 Device 2: 0x02C0]
• Device n Endpoint 5 Control Register [Device 1: 0x0250 Device 2: 0x02D0]
• Device n Endpoint 6 Control Register [Device 1: 0x0260 Device 2: 0x02E0]
• Device n Endpoint 7 Control Register [Device 1: 0x0270 Device 2: 0x02F0]
Table
IN/OUT
Enable
Ignore
R/W
15
X
X
7
-
35.
Sequence
Select
R/W
14
X
X
6
-
Figure 38. Device n Endpoint n Control Register
Enable
R/W
Stall
13
X
X
5
-
Enable
0x02n0
0x02n2
0x02n4
0x02n8
0xC084/0xC0A4
0xC08C/0xC0AC
0xC08E/0xC0AE
0xC090/0xCB0
Address (Device 1/Device 2)
0x02n6
0xC092/0xC0B2
0xC094/0xC0B4
R/W
ISO
12
X
X
4
-
IN/OUT Ignore Enable (Bit 7)
The IN/OUT Ignore Enable bit forces endpoint 0 (EP0) to
ignore all IN and OUT requests. This bit should be set so that
EP0 only excepts Setup packets at the start of each transfer.
This bit must be cleared to except IN/OUT transactions. This
bit only applies to EP0.
1: Ignore IN/OUT requests
0: Do not ignore IN/OUT requests
Reserved
Interrupt
Enable
NAK
R/W
11
X
X
3
-
Direction
Select
R/W
10
X
X
2
-
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
W
R/W
X
X
9
1
-
CY7C67300
Page 38 of 98
Enable
R/W
Arm
X
X
8
0
-
[+] Feedback