CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 26

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
Watchdog Timer Register [0xC00C] [R/W]
Register Description
The Watchdog Timer Register provides status and control over
the Watchdog timer. The Watchdog timer can also interrupt the
processor.
Timeout Flag (Bit 5)
The Timeout Flag bit indicates if the Watchdog timer has
expired. The processor can read this bit after exiting a reset to
determine if a Watchdog timeout occurred. This bit is cleared
on the next external hardware reset.
1: Watchdog timer expired.
0: Watchdog timer did not expire.
Period Select (Bits [4:3])
The Period Select field is defined in
expires before the Reset Strobe bit is set, the internal
processor will be reset.
Table 28.Period Select Definition
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Period Select[4:3]
00
01
10
11
R/W
R/W
15
0
7
0
...Reserved
R/W
R/W
14
0
6
0
WDT Period Value
Table
22.0 ms
66.0 ms
1.4 ms
5.5 ms
Figure 23. Watchdog Timer Register
28. If this time
Timeout
Flag
R/W
R/W
13
0
5
0
R/W
R/W
12
4
0
0
Reserved...
Lock Enable (Bit 2)
The Lock Enable bit does not allow any writes to this register
until a reset. In doing so the Watchdog timer can be set up and
enabled permanently so that it can only be cleared on reset
(the WDT Enable bit is ignored).
1: Watchdog timer permanently set
0: Watchdog timer not permanently set
WDT Enable (Bit 1)
The WDT Enable bit enables or disables the Watchdog timer.
1: Enable Watchdog timer operation
0: Disable Watchdog timer operation
Reset Strobe (Bit 0)
The Reset Strobe is a write-only bit that resets the Watchdog
timer count. It must be set to ‘1’ before the count expires to
avoid a Watchdog trigger
1: Reset Count
Reserved
All reserved bits should be written as ‘0’.
Period
Select
R/W
R/W
11
3
0
0
Enable
Lock
R/W
R/W
10
2
0
0
Enable
WDT
R/W
R/W
1
0
9
0
CY7C67300
Page 26 of 98
Strobe
Reset
R/W
W
0
0
8
0
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