CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 69

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
Receive Interrupt Flag (Bit 2)
The Receive Interrupt Flag is a read-only bit that indicates if a
byte mode receive interrupt has triggered.
1: Indicates a byte mode receive interrupt has triggered
0: Indicates a byte mode receive interrupt has not triggered
Transmit Interrupt Flag (Bit 1)
The Transmit Interrupt Flag is a read-only bit that indicates a
byte mode transmit interrupt has triggered.
SPI Interrupt Clear Register [0xC0D0] [W]
Register Description
The SPI Interrupt Clear Register is a write-only register that
allows the SPI Transmit and SPI Transfer Interrupts to be
cleared.
Transmit Interrupt Clear (Bit 1)
The Transmit Interrupt Clear bit is a write-only bit that will clear
the byte mode transmit interrupt. This bit is self-clearing.
1: Clear the byte mode transmit interrupt
0: No function
SPI CRC Control Register [0xC0D2] [R/W]
Register Description
The SPI CRC Control Register provides control over the CRC source and polynomial value.
CRC Mode (Bits [15:14)
The CRCMode field selects the CRC polynomial as defined in
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
R/W
15
15
0
7
0
0
7
0
-
-
-
CRC Mode
R/W
14
14
0
6
0
0
6
0
-
-
-
Figure 75. SPI Interrupt Clear Register
Figure 76. SPI CRC Control Register
Enable
CRC
R/W
13
13
0
5
0
0
5
0
-
-
-
Reserved
Clear
CRC
R/W
12
12
Table
0
4
0
0
4
0
-
-
-
...Reserved
1: Indicates a byte mode transmit interrupt has triggered
0: Indicates a byte mode transmit interrupt has not triggered
Transfer Interrupt Flag (Bit 0)
The Transfer Interrupt Flag is a read-only bit that indicates a
block mode interrupt has triggered.
1: Indicates a block mode interrupt has triggered
0: Indicates a block mode interrupt has not triggered
Transfer Interrupt Clear (Bit 0)
The Transfer Interrupt Clear bit is a write-only bit that will clear
the block mode interrupt. This bit is self-clearing.
1: Clear the block mode interrupt
0: No function
Reserved
All reserved bits should be written as ‘0’.
Reserved
46.
Receive
CRC
R/W
11
11
0
3
0
0
3
0
-
-
-
One in
CRC
10
10
0
2
0
R
0
2
0
-
-
-
Transmit
Interrupt
Zero in
Clear
CRC
W
9
0
1
0
R
-
9
0
1
0
-
CY7C67300
Page 69 of 98
Reserved...
Interrupt
Transfer
Clear
W
8
0
0
0
-
8
0
0
0
-
-
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