CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 41

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
Device n Endpoint n Status Register [R/W]
Register Description
The Device n Endpoint n Status Register provides packet
status information for the last transaction received or trans-
mitted. This register is updated in hardware and does not need
to be cleared by firmware. There are a total of eight endpoints
for each of the two ports. All endpoints have the same
definition for their Device n Endpoint n Status Register.
The Device n Endpoint n Status Register is a memory based
register that should be initialized to 0x0000 before USB Device
operations are initiated. After initialization, this register should
not be written to again.
Overflow Flag (Bit 11)
The Overflow Flag bit indicates that the received data in the
last data transaction exceeded the maximum length specified
in the Device n Endpoint n Count Register. The Overflow Flag
should be checked in response to a Length Exception signified
by the Length Exception Flag set to ‘1’.
1: Overflow condition occurred
0: Overflow condition did not occur
Underflow Flag (Bit 10)
The Underflow Flag bit indicates that the received data in the
last data transaction was less then the maximum length
specified in the Device n Endpoint n Count Register. The
Underflow Flag should be checked in response to a Length
Exception signified by the Length Exception Flag set to ‘1’.
1: Underflow condition occurred
0: Underflow condition did not occur
OUT Exception Flag (Bit 9)
The OUT Exception Flag bit indicates when the device
received an OUT packet when armed for an IN.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Device n Endpoint 0 Status Register [Device 1: 0x0206 Device 2: 0x0286]
• Device n Endpoint 1 Status Register [Device 1: 0x0216 Device 2: 0x0296]
• Device n Endpoint 2 Status Register [Device 1: 0x0226 Device 2: 0x02A6]
• Device n Endpoint 3 Status Register [Device 1: 0x0236 Device 2: 0x02B6]
• Device n Endpoint 4 Status Register [Device 1: 0x0246 Device 2: 0x02C6]
• Device n Endpoint 5 Status Register [Device 1: 0x0256 Device 2: 0x02D6]
• Device n Endpoint 6 Status Register [Device 1: 0x0266 Device 2: 0x02E6]
• Device n Endpoint 7 Status Register [Device 1: 0x0276 Device 2: 0x02F6]
Flag
R/W
Stall
15
X
7
X
-
NAK
Flag
R/W
14
6
X
X
-
Reserved
Figure 41. Device n Endpoint n Status Register
Exception Flag
Length
R/W
13
X
-
X
5
12
X
-
Setup
Flag
R/W
X
4
1: Received OUT when armed for IN
0: Received IN when armed for IN
IN Exception Flag (Bit 8)
The IN Exception Flag bit indicates when the device received
an IN packet when armed for an OUT.
1: Received IN when armed for OUT
0: Received OUT when armed for OUT
Stall Flag (Bit 7)
The Stall Flag bit indicates that a Stall packet was sent to the
host.
1: Stall packet was sent to the host
0: Stall packet was not sent
NAK Flag (Bit 6)
The NAK Flag bit indicates that a NAK packet was sent to the
host.
1: NAK packet was sent to the host
0: NAK packet was not sent
Length Exception Flag (Bit 5)
The Length Exception Flag bit indicates the received data in
the data stage of the last transaction does not equal the
maximum Endpoint Count specified in the Device n Endpoint
n Count Register. A Length Exception can either mean an
overflow or underflow and the Overflow and Underflow flags
(bits 11 and 10 respectively) should be checked to determine
which event occurred.
1: An overflow or underflow condition occurred
0: An overflow or underflow condition did not occur
Overflow
Flag
R/W
11
Sequence
X
Flag
R/W
X
3
Underflow
Flag
R/W
10
Timeout
X
Flag
R/W
X
2
Exception Flag
OUT
R/W
X
Error
9
Flag
R/W
X
1
CY7C67300
Page 41 of 98
Exception Flag
R/W
ACK
Flag
R/W
IN
X
8
X
0
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