CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 17

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
Bank Register [0xC002] [R/W]
Register Description
The Bank Register maps registers R0–R15 into RAM. The eleven MSBs of this register are used as a base address for registers
R0–R15. A register address is automatically generated by:
For example, if the Bank Register is left at its default value of 0x0100, and R2 is read, then the physical address 0x0102 will be
read. Refer to
Table 22.Bank Register Example
Address (Bits [15:4])
The Address field is used as a base address for all register addresses to start from.
Reserved
All reserved bits should be written as ‘0’.
Hardware Revision Register [0xC004] [R]
Register Description
The Hardware Revision Register is a read-only register that indicates the silicon revision number. The first silicon revision is
represented by 0x0101. This number is increased by one for each new silicon revision.
Revision (Bits [15:0])
The Revision field contains the silicon revision number.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
1. Shifting the four LSBs of the register address left by 1.
2. ORing the four shifted bits of the register address with the twelve MSBs of the Bank Register.
3. Forcing the LSB to zero.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
RAM Location
Table 22
Register
Bank
R14
R/W
R/W
15
15
R
X
R
X
0
7
0
7
for details.
...Address
R/W
R/W
14
14
R
X
R
X
0
6
0
6
R/W
R/W
13
Figure 13. Revision Register
13
R
R
X
X
0
5
0
5
Figure 12. Bank Register
0x000E << 1 = 0x001C
Hex Value
0x011C
0x0100
R/W
12
12
R
R
X
X
4
X
0
4
-
Revision...
...Revision
Address...
R/W
11
11
R
R
X
X
3
X
0
3
-
Reserved
R/W
10
10
R
X
R
X
X
2
0
2
-
0000 0001 0000 0000
0000 0000 0001 1100
0000 0001 0001 1100
Binary Value
R/W
R
X
R
X
X
9
1
9
0
1
-
CY7C67300
Page 17 of 98
R/W
R
X
R
X
X
8
0
8
1
0
-
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