CY7C67300-100AXA Cypress Semiconductor Corp, CY7C67300-100AXA Datasheet - Page 30

• Manufacturer Part Number: CY7C67300-100AXA
• Description: IC,Peripheral (Multifunction) Controller,QFP,100PIN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXA

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-08015 Rev. *G
Sequence Select (Bit 6)
The Sequence Select bit sets the data toggle for the next
packet. This bit has no effect on receiving data packets;
sequence checking must be handled in firmware.
1: Send DATA1
0: Send DATA0
Sync Enable (Bit 5)
The Sync Enable bit synchronizes the transfer with the SOF
packet in full-speed mode and the EOP packet in low-speed
mode.
1: The next enabled packet will be transferred after the SOF
or EOP packet is transmitted
0: The next enabled packet will be transferred as soon as the
SIE is free
Host n Address Register [R/W]
Register Description
The Host n Address Register is used as the base pointer into
memory space for the current host transactions.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Host 1 Address Register 0xC082.
• Host 2 Address Register 0xC0A2.
R/W
R/W
15
0
7
0
R/W
R/W
14
0
6
0
Figure 27. Host n Address Register
R/W
R/W
13
0
5
0
R/W
R/W
12
0
4
0
ISO Enable (Bit 4)
The ISO Enable bit enables or disables an Isochronous trans-
action.
1: Enable Isochronous transaction
0: Disable Isochronous transaction
Arm Enable (Bit 0)
The Arm Enable bit arms an endpoint and starts a transaction.
This bit is automatically cleared to ‘0’ when a transaction is
complete.
1: Arm endpoint and begin transaction
0: Endpoint disarmed
Reserved
All reserved bits should be written as ‘0’.
Address (Bits [15:0])
The Address field sets the address pointer into internal RAM
or ROM.
Address...
...Address
R/W
R/W
11
0
3
0
R/W
R/W
10
0
2
0
R/W
R/W
9
0
1
0
CY7C67300
Page 30 of 98
R/W
R/W
8
0
0
0
[+] Feedback