YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 961

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 21.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI
Bit Rate of Host
9,600 bps
19,200 bps
(2)
The overview of the state transition diagram after boot mode is initiated is shown in figure 21.8.
1. Bit rate adjustment
2. Waiting for inquiry set command
3. Automatic erasure of all user MAT and user boot MAT
4. Waiting for programming/erasing command
After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host.
For inquiries about user-MAT size and configuration, MAT start address, and support state, the
required information is transmitted to the host.
After inquiries have finished, all user MAT and user boot MAT are automatically erased.
⎯ When the program preparation notice is received, the state for waiting program data is
⎯ When the erasure preparation notice is received, the state for waiting erase-block data is
State Transition Diagram
Programming finished area
entered. The programming start address and program data must be transmitted following
the programming command. When programming is finished, the programming start address
must be set to H'FFFFFFFF and transmitted. Then the state for waiting program data is
returned to the state of programming/erasing command wait. Before reprogramming erased
blocks containing a programming finished area for which the programming finished
command has been issued, make sure to erase the corresponding erased blocks.
entered. The erase-block number must be transmitted following the erasing command.
When the erasure is finished, the erase-block number must be set to H'FF and transmitted.
Then the state for waiting erase-block data is returned to the state for waiting
:
System Clock Frequency
8 to 25 MHz
8 to 25 MHz
:
EB9
EB10
EB11
EB12
Before reprogramming erased blocks containing a programming
finished area (EB10 and EB11), the corresponding erased
blocks (EB10 and EB11) should be erased.
Section 21 Flash Memory (0.18-μm F-ZTAT Version)
Rev.7.00 Mar. 18, 2009 page 893 of 1136
REJ09B0109-0700