YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 271

Manufacturer Part Number

KIT DEV EVAL H8S/2378 LCD

Manufacturer

Renesas Electronics America

Main Purpose

Displays, LCD Controller

Yes, MCU, 16-Bit

Utilized Ic / Part

Primary Attributes

5.7" QVGA, Touch Screen

Secondary Attributes

Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

With DRAM, in addition to full access (normal access) in which data is accessed by outputting a

row address for each access, a fast page mode is also provided which can be used when making

consecutive accesses to the same row address. This mode enables fast (burst) access of data by

simply changing the column address after the row address has been output. Burst access can be

selected by setting the BE bit to 1 in DRAMCR.

Burst Access (Fast Page Mode): Figures 6.30 and 6.31 show the operation timing for burst

access. When there are consecutive access cycles for DRAM space, the CAS signal and column

address output cycles (two states) continue as long as the row address is the same for consecutive

access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in

Burst Operation

(Address shift size

set to 10 bits)

Figure 6.29 Example of 2-CAS DRAM Connection

Rev.7.00 Mar. 18, 2009 page 203 of 1136

1-Mbyte × 16-bit configuration

2-CAS type 16-Mbit DRAM

10-bit column address

Section 6 Bus Controller (BSC)

Row address input:

Column address input:

REJ09B0109-0700