YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 475

Manufacturer Part Number

KIT DEV EVAL H8S/2378 LCD

Manufacturer

Renesas Electronics America

Main Purpose

Displays, LCD Controller

Yes, MCU, 16-Bit

Utilized Ic / Part

Primary Attributes

5.7" QVGA, Touch Screen

Secondary Attributes

Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Auto Request/Burst Mode/Normal Transfer Mode: When the EDA bit is set to 1 in EDMDR,

an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it

continues (as a burst) until the transfer end condition is satisfied.

If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another

Transfer requests for other channels are held pending until the end of transfer on the current

Figures 8.31 to 8.34 show operation timing examples for various conditions.

CPU cycle CPU cycle

Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode

Figure 8.32 Auto Request/Burst Mode/Normal Transfer Mode

(CPU Cycles/Dual Address Mode/BGUP = 0)

(CPU Cycles/Dual Address Mode/BGUP = 1)

Rev.7.00 Mar. 18, 2009 page 407 of 1136

Section 8 EXDMA Controller (EXDMAC)

Last transfer cycle

REJ09B0109-0700