YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 1047

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

All-module-clocks-stop mode is cleared by an external interrupt (NMI, IRQ0 to IRQ7 pins), RES
pin input, or an internal interrupt (8-bit timer, watchdog timer), and the CPU returns to the normal
program execution state via the exception handling state. All-module-clocks-stop mode is not
cleared if interrupts are disabled, if interrupts other than NMI are masked by the CPU, or if the
relevant interrupt is designated as a DTC activation source.
When the STBY pin is driven low, a transition is made to hardware standby mode.
24.3
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 24.3 shows the state of the φ pin in each processing state.
Table 24.3 φ Pin State in Each Processing State
Register Setting
DDR
0
1
1
24.4
24.4.1
In software standby mode, I/O port states are retained. Therefore, there is no reduction in current
dissipation for the output current when a high-level signal is output.
24.4.2
Current dissipation increases during the oscillation stabilization standby period.
PSTOP
X
0
1
φ Clock Output Control
Usage Notes
I/O Port Status
Current Dissipation during Oscillation Stabilization Standby Period
Normal operating
state
High impedance
φ output
Fixed high
Sleep mode
High impedance High impedance
φ output
Fixed high
Software
standby mode
Fixed high
Fixed high
Rev.7.00 Mar. 18, 2009 page 979 of 1136
Section 24 Power-Down Modes
Hardware
standby mode
High impedance
High impedance
High impedance
REJ09B0109-0700
All-module-
clocks-stop
mode
High impedance
φ output
Fixed high