YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 317

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.9
6.9.1
When this LSI accesses external address space, it can insert an idle cycle (T
in the following three cases: (1) when read accesses in different areas occur consecutively, (2)
when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs
immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the
IDLC bit in BCR. By inserting an idle cycle it is possible, for example, to avoid data collisions
between ROM, etc., with a long output floating time, and high-speed memory, I/O interfaces, and
so on.
Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.65 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
CS (area A)
CS (area B)
Address bus
Idle Cycle
Operation
Data bus
RD
φ
(a) No idle cycle insertion
(ICIS1 = 0)
T
1
Bus cycle A
Long output floating time
Figure 6.65 Example of Idle Cycle Operation
T
2
(Consecutive Reads in Different Areas)
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
CS (area A)
CS (area B)
Data bus
RD
Rev.7.00 Mar. 18, 2009 page 249 of 1136
φ
T
1
Bus cycle A
(b) Idle cycle insertion
Section 6 Bus Controller (BSC)
(ICIS1 = 1, initial value)
T
2
T
3
Idle cycle
i
) between bus cycles
T
Bus cycle B
i
REJ09B0109-0700
T
1
T
2