YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 219

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3.5
CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip
select signals (CSn) and address signals is to be extended. Extending the assertion period of the
CSn and address signals allows flexible interfacing to external I/O devices.
• CSACRH
Bit
7
6
5
4
3
2
1
0
• CSACRL
Bit
7
6
5
4
3
2
1
0
Bit Name
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
Bit Name
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
CS Assertion Period Control Registers H, L (CSACRH, CSACRL)
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
CS and Address Signal Assertion Period Control 1
These bits specify whether or not the T
be inserted (see figure 6.3). When an area for
which the CSXHn bit is set to 1 is accessed, a one-
state T
signals are asserted, is inserted before the normal
access cycle.
0: In area n basic bus interface access, the CSn
1: In area n basic bus interface access, the CSn
Description
CS and Address Signal Assertion Period Control 2
These bits specify whether or not the T
shown in figure 6.3 is to be inserted. When an area
for which the CSXTn bit is set to 1 is accessed, a
one-state T
address signals are asserted, is inserted after the
normal access cycle.
0: In area n basic bus interface access, the CSn
1: In area n basic bus interface access, the CSn
and address assertion period (T
extended
and address assertion period (T
and address assertion period (T
extended
and address assertion period (T
h
cycle, in which only the CSn and address
Rev.7.00 Mar. 18, 2009 page 151 of 1136
t
cycle, in which only the CSn and
Section 6 Bus Controller (BSC)
REJ09B0109-0700
h
h
t
t
) is not
) is extended
) is not
) is extended
h
t
cycle
cycle is to
(n = 7 to 0)
(n = 7 to 0)