YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 488

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 8 EXDMA Controller (EXDMAC)
8.5
EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area
overflow interrupts. Table 8.4 shows the interrupt sources and their priority order.
Table 8.4
Interrupt
EXDMTEND2
EXDMTEND3
Interrupt sources can be enabled or disabled by means of the EDIE bit in EDMDR for the relevant
channel, and can be sent to the interrupt controller independently. The relative priority order of the
channels is determined by the interrupt controller (see table 8.4).
Figure 8.45 shows the transfer end interrupt logic. A transfer end interrupt is generated whenever
the EDIE bit is set to 1 while the IRF bit is set to 1 in EDMDR.
Interrupt source settings are made individually with the interrupt enable bits in the registers for the
relevant channels. The transfer counter’s transfer end interrupt is enabled or disabled by means of
the TCEIE bit in EDMDR, the source address register repeat area overflow interrupt by means of
the SARIE bit in EDACR, and the destination address register repeat area overflow interrupt by
means of the DARIE bit in EDACR. When an interrupt source occurs while the corresponding
interrupt enable bit is set to 1, the IRF bit in EDMDR is set to 1. The IRF bit is set by all interrupt
sources indiscriminately.
The transfer end interrupt can be cleared either by clearing the IRF bit to 0 in EDMDR within the
interrupt handling routine, or by re-setting the transfer counter and address registers and then
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REJ09B0109-0700
Interrupt Sources
Interrupt Sources and Priority Order
EDIE bit
IRF bit
Interrupt source
Transfer end indicated by channel 2 transfer counter
Channel 2 source address repeat area overflow
Channel 2 destination address repeat area overflow
Transfer end indicated by channel 3 transfer counter
Channel 3 source address repeat area overflow
Channel 3 destination address repeat area overflow
Figure 8.45 Transfer End Interrupt Logic
Transfer end interrupt
Interrupt Priority
High
Low