YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 403

Manufacturer Part Number

KIT DEV EVAL H8S/2378 LCD

Manufacturer

Renesas Electronics America

Main Purpose

Displays, LCD Controller

Yes, MCU, 16-Bit

Utilized Ic / Part

Primary Attributes

5.7" QVGA, Touch Screen

Secondary Attributes

Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Full Address Mode (Block Transfer Mode): Figure 7.21 shows a transfer example in which

TEND output is enabled and word-size full address mode transfer (block transfer mode) is

performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.

A one-block transfer is performed for a single transfer request, and after the transfer the bus is

released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.

In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-

state DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is generated

during data transfer, block transfer operation is not affected until data transfer for one block has

DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel

for which the DREQ pin is selected.

Figure 7.22 shows an example of normal mode transfer activated by the DREQ pin falling edge.

Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)

Block transfer

Rev.7.00 Mar. 18, 2009 page 335 of 1136

Section 7 DMA Controller (DMAC)

Last block transfer

REJ09B0109-0700