YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 36

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.5 Usage Notes ....................................................................................................................... 651
Section 13 8-Bit Timers (TMR) ........................................................................ 653
13.1 Features .............................................................................................................................. 653
13.2 Input/Output Pins ............................................................................................................... 655
13.3 Register Descriptions ......................................................................................................... 655
13.4 Operation............................................................................................................................ 663
13.5 Operation Timing............................................................................................................... 664
13.6 Operation with Cascaded Connection ................................................................................ 668
13.7 Interrupt Sources ................................................................................................................ 669
13.8 Usage Notes ....................................................................................................................... 670
Rev.7.00 Mar. 18, 2009 page xxxiv of lxvi
REJ09B0109-0700
12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase
12.4.7 Inverted Pulse Output ........................................................................................... 650
12.4.8 Pulse Output Triggered by Input Capture ............................................................. 651
12.5.1 Module Stop Mode Setting ................................................................................... 651
12.5.2 Operation of Pulse Output Pins............................................................................. 651
13.3.1 Timer Counter (TCNT)......................................................................................... 656
13.3.2 Time Constant Register A (TCORA).................................................................... 656
13.3.3 Time Constant Register B (TCORB) .................................................................... 656
13.3.4 Timer Control Register (TCR) .............................................................................. 657
13.3.5 Timer Control/Status Register (TCSR) ................................................................. 659
13.4.1 Pulse Output.......................................................................................................... 663
13.5.1 TCNT Incrementation Timing .............................................................................. 664
13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs .................. 665
13.5.3 Timing of Timer Output when Compare-Match Occurs....................................... 666
13.5.4 Timing of Compare Match Clear .......................................................................... 666
13.5.5 Timing of TCNT External Reset........................................................................... 667
13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 667
13.6.1 16-Bit Counter Mode ............................................................................................ 668
13.6.2 Compare Match Count Mode................................................................................ 668
13.7.1 Interrupt Sources and DTC Activation ................................................................. 669
13.7.2 A/D Converter Activation..................................................................................... 669
13.8.1 Contention between TCNT Write and Clear......................................................... 670
13.8.2 Contention between TCNT Write and Increment ................................................. 671
13.8.3 Contention between TCOR Write and Compare Match ....................................... 672
13.8.4 Contention between Compare Matches A and B .................................................. 673
13.8.5 Switching of Internal Clocks and TCNT Operation.............................................. 673
13.8.6 Mode Setting with Cascaded Connection ............................................................. 675
13.8.7 Interrupts in Module Stop Mode........................................................................... 675
Complementary Non-Overlapping Output) .......................................................... 648