YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 922

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 20 Flash Memory (0.35-μm F-ZTAT Version)
20.8
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
20.8.1
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset (including an overflow reset by the WDT) or
standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2
(FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2) are initialized. In a
reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation
stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the
RES pulse width specified in the AC Characteristics section.
20.8.2
Protection can be implemented against programming/erasing of all flash memory blocks by
clearing the SWE bit in FLMCR1 to 0 by software (these operations must be executed in the on-
chip RAM or external memory). When protection is in effect, setting the P or E bit in FLMCR1
does not cause a transition to program mode or erase mode. By setting the erase block register 1
(EBR1) and erase block register 2 (EBR2), erase protection can be set for individual blocks.
When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks.
20.8.3
In error protection, an error is detected when the CPU’s runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase
operation prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When flash memory is read during programming/erasing (including a vector read or instruction
• When an exception handling (excluding a reset) is started during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
• When the CPU releases the bus during programming/erasing
Rev.7.00 Mar. 18, 2009 page 854 of 1136
REJ09B0109-0700
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Program/Erase Protection
Hardware Protection
Software Protection
Error Protection