YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 724

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 13 8-Bit Timers (TMR)
13.3.1
TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be
accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a
clock. TCNT can be cleared by an external reset input or by a compare match signal A or B.
Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When
TCNT overflows from H'FF to H'00, OVF in TCSR is set to 1. TCNT is initialized to H'00.
13.3.2
TCORA is 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction.
The value in TCORA is continually compared with the value in TCNT. When a match is detected,
the corresponding CMFA flag in TCSR is set to 1. Note, however, that comparison is disabled
during the T
The timer output from the TMO pin can be freely controlled by this compare match signal
(compare match A) and the settings of bits OS1 and OS0 in TCSR.
TCORA is initialized to H'FF.
13.3.3
TCORB is 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFB flag in TCSR is set to 1. Note, however, that comparison is disabled during
the T
The timer output from the TMO pin can be freely controlled by this compare match signal
(compare match B) and the settings of bits OS3 and OS2 in TCSR.
TCORB is initialized to H'FF.
Rev.7.00 Mar. 18, 2009 page 656 of 1136
REJ09B0109-0700
2
state of a TCOBR write cycle.
Timer Counter (TCNT)
Time Constant Register A (TCORA)
Time Constant Register B (TCORB)
2
state of a TCORA write cycle.