YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 425

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

However, if the last transfer cycle and a CBR refresh occur simultaneously, note that although the
CBR refresh and the last transfer cycle may be executed consecutively, TEND may also go low in
this case for the refresh cycle.
7.7.5
DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.
The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer
is enabled is performed on detection of a low level.
switches to [2].
switches to [1].
Internal write signal
Internal read signal
Activation by Falling Edge on DREQ Pin
External address
Figure 7.41 Example in which Low Level Is Not Output at TEND Pin
Internal address
HWR, LWR
TEND
φ
External write by CPU, etc.
Not output
DMA
read
Rev.7.00 Mar. 18, 2009 page 357 of 1136
Section 7 DMA Controller (DMAC)
DMA
write
REJ09B0109-0700